M53D128168A-2E Datasheet, PDF (10/47 Pages) Elite Semiconductor Memory Technology Inc. – Internal pipelined double-data-rate architecture, two data

ESMT
M53D128168A (2E)
Operation Temperature Condition -40°C~85°C
Basic Functionality
Power-Up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE at a high state (all other inputs may be undefined.)
- Apply V_DD before or at the same time as V_DDQ.
2. Start clock and maintain stable condition for a minimum.
3. The minimum of 200us after stable power and clock (CLK, CLK ), apply NOP.
4. Issue precharge commands for all banks of the device.
5. Issue 2 or more auto-refresh commands.
6. Issue mode register set command to initialize the mode register.
7. Issue extended mode register set command to set PASR and DS.
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14 15 16 17 18
19
20
CLOCK
CKE
High level is necessary
CS
tRP
RAS
tRFC
tRFC
tMRD
tMRD
CAS
ADDR
BA1
BA0
Key
Key
RA
BS
BS
A10/AP
RA
DQ
High-Z
WE
DQM
High level is necessary
Precharge
(All Banks)
Auto Refresh
Auto Refresh
Elite Semiconductor Memory Technology Inc.
Mode Register Set
Row Active
Extended Mode
Register Set
: Don't care
Publication Date : Jul. 2012
Revision : 1.0
10/47