F59D4G81A Datasheet, PDF (1/54 Pages) Elite Semiconductor Memory Technology Inc. – Voltage Supply: 1.8V (1.7V ~ 1.95V)

ESMT
Flash
FEATURES
 Voltage Supply: 1.8V (1.7V ~ 1.95V)
 Organization
x8:
- Memory Cell Array: (512M + 8M) x 8bit
- Data Register: (2K + 64) x 8bit
x16:
- Memory Cell Array: (256M + 4M) x 16bit
- Data Register: (1K + 32) x 16bit
 Automatic Program and Erase
x8:
- Page Program: (2K + 64) Byte
- Block Erase: (128K + 4K) Byte
x16:
- Page Program: (1K + 32) Word
- Block Erase: (64K + 2K) Word
 Page Read Operation
- Page Size: (2K + 64) Byte (x8)
Page Size: (1K + 32) Word (x16)
- Random Read: 25us (Max.)
- Serial Access: 45ns (Min.)
 Memory Cell: 1bit/Memory Cell
 Fast Write Cycle Time
- Program time: 350us (Typ.)
- Block Erase time: 3.5ms (Typ.)
F59D4G81A / F59D4G161A
4 Gbit (512M x 8 / 256M x 16)
1.8V NAND Flash Memory
 Command/Address/Data Multiplexed I/O Port
 Hardware Data Protection
- Program/Erase Lockout During Power Transitions
 Reliable CMOS Floating Gate Technology
- ECC Requirement: x8 - 4bit/512Byte
x16 - 4bit/256Word
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
 Command Register Operation
 Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
 NOP: 4 cycles
 Cache Program/Read Operation
 Copy-Back Operation
 Two-Plane Operation
 EDO mode
 Bad-Block-Protect
ORDERING INFORMATION
Product ID
Speed
Package
x8:
F59D4G81A -45TG
45 ns
48 pin TSOPI
x16:
F59D4G161A -45TG 45 ns
48 pin TSOPI
Comments
Pb-free
Pb-free
GENERAL DESCRIPTION
The device is a 512Mx8bit with spare 16Mx8bit capacity (or
256Mx16bit with spare 8Mx16bit capacity). The device is offered
in 1.8V V_CC Power Supply. Its NAND cell provides the most
cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased
independently so it is possible to preserve valid data while old
data is erased.
The device contains 4096 blocks, composed by 64 pages
consisting in two NAND structures of 32 series connected Flash
cells. A program operation allows to write the 1056-Word page in
typical 350us and an erase operation can be performed in typical
3.5ms on a 128K-Byte for X8 device block (or 64K-Word for X16
device block).
Data in the page mode can be read out at 45ns cycle time per
Elite Semiconductor Memory Technology Inc.
Word. The I/O pins serve as the ports for address and command
inputs as well as data input/output. The copy back function
allows the optimization of defective blocks management: when a
page program operation fails the data can be directly
programmed in another page inside the same array section
without the time consuming serial data insertion phase. The
cache program feature allows the data insertion in the cache
register while the data register is copied into the Flash array.
This pipelined program operation improves the program
throughput when long files are written inside the memory. A
cache read feature is also implemented. This feature allows to
dramatically improving the read throughput when consecutive
pages have to be streamed out. This device includes extra
feature: Automatic Read at Power Up.
Publication Date: May 2014
Revision: 1.4
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