EN25Q16 Datasheet, PDF(9/40 Page) Eon Silicon Solution Inc. – 16 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

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EN25Q16 Datasheet, PDF (9/40 Pages) Eon Silicon Solution Inc. – 16 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

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EN25Q16

z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set

the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:

â Power-up

â Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction

completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction

completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction

completion

z The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only.

This is the Software Protected Mode (SPM).

z The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register

Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).

z In addition to the low power consumption feature, the Deep Power-down mode offers extra

software protection from inadvertent Write, Program and Erase instructions, as all instructions are

ignored except one particular instruction (the Release from Deep Power-down instruction).

Table 3. Protected Area Sizes Sector Organization

Status Register

Content

BP2 BP1 BP0

Bit Bit Bit

Memory Content

Protected Areas

Addresses

None

Block 0 to 30

Block 0 to 29

Block 0 to 27

Block 0 to 23

Block 0 to 15

All

None

000000h-1EFFFFh

000000h-1DFFFFh

000000h-1BFFFFh

000000h-17FFFFh

000000h-0FFFFFh

000000h-1FFFFFh

Density (KB)

None

1984KB

1920KB

1792KB

1536KB

1024KB

2048KB

Portion

None

Lower 31/32

Lower 15/16

Lower 7/8

Lower 3/4

Lower 1/2

All

INSTRUCTIONS

All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial

Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is

driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,

on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).

The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction

code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by

both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has

been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed

(Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, and Read Device ID

(RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select

(CS#) can be driven High after any bit of the data-out sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write

Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)

instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction

is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock

pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at

any time the input byte is not a full byte, nothing will happen and WEL will not be reset.

In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down

(RES ) minimum number of bytes specified has to be given, without which, the command will be

ignored.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. E, Issue Date: 2009/10/21

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