EN25B05 Datasheet, PDF(8/30 Page) Eon Silicon Solution Inc. – 512 Kbit Serial Flash Memory with Boot and Parameter Sectors

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EN25B05 Datasheet, PDF (8/30 Pages) Eon Silicon Solution Inc. – 512 Kbit Serial Flash Memory with Boot and Parameter Sectors

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INSTRUCTIONS

EN25B05

All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial

Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven

Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on

Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).

The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code.

Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or

none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted

in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read

Status Register (RDSR) or Release from Deep Power-down, and Read Device ID (RDI) instruction, the

shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High

after any bit of the data-out sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR),

Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (CS#)

must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed.

That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#)

being driven Low is an exact multiple of eight.

All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase

cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues

unaffected.

Table 4. Instruction Set

Instruction Name

Write Enable

Write Disable

Read Status

Write Status

Read Data

Fast Read

Page Program

Sector Erase

Bulk Erase

Deep Power-down

Release from Deep

Power-down, and

read Device ID

Release from Deep

Power-down

Manufacturer/

Device ID

Read Identification

Byte 1

Code

06h

04h

05h

01h

03h

0Bh

02h

D8h

C7h

B9h

ABh

90h

9Fh

Byte 2

Byte 3

Byte 4 Byte 5 Byte 6

n-Bytes

(S7-S0)(1)

S7-S0

A23-A16

A15-A8

continuous

(2)

A7-A0

(D7-D0)

dummy

D7-D0

(Next byte)

(D7-D0)

(Next byte)

continuous

(Next Byte)

continuous

(4)

dummy

dummy dummy (ID7-ID0)

dummy

dummy 00h

(M7-M0) (ID7-ID0)

(5)

(M7-M0) (ID15-ID8) (ID7-ID0)

Notes:

1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis â( )â indicate data being read from

the device on the DO pin.

2. The Status Register contents will repeat continuously until CS# terminate the instruction.

3. All sectors may use any address within the sector.

4. The Device ID will repeat continuously until CS# terminate the instruction.

5. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminate the instruction.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. B, Issue Date: 2006/12/26

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