EN25P32 Datasheet, PDF (6/34 Pages) Eon Silicon Solution Inc. – 32 Mbit Uniform Sector, Serial Flash Memory

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1A0000h – 1AFFFFh
190000h – 19FFFFh
180000h – 18FFFFh
170000h – 17FFFFh
160000h – 16FFFFh
150000h – 15FFFFh
140000h – 14FFFFh
130000h – 13FFFFh
120000h – 12FFFFh
110000h – 11FFFFh
100000h – 10FFFFh
0F0000h – 0FFFFFh
0E0000h – 0EFFFFh
0D0000h – 0DFFFFh
0C0000h – 0CFFFFh
0B0000h – 0BFFFFh
0A0000h – 0AFFFFh
090000h – 09FFFFh
080000h – 08FFFFh
070000h – 07FFFFh
060000h – 06FFFFh
050000h – 05FFFFh
040000h – 04FFFFh
030000h – 03FFFFh
020000h – 02FFFFh
010000h – 01FFFFh
000000h – 00FFFFh
EN25P32
OPERATING FEATURES
SPI Modes
The EN25P32 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0
(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure
3, concerns the normal state of the SCK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0 the SCK signal is normally low. For Mode 3 the SCK
signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the SCK.
Data output on the DO pin is clocked out on the falling edge of SCK.
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/10/18