EN25F05 Datasheet, PDF(6/31 Page) Eon Silicon Solution Inc. – 512 Kbit Serial Flash Memory with 4Kbytes Uniform Sector

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EN25F05 Datasheet, PDF (6/31 Pages) Eon Silicon Solution Inc. – 512 Kbit Serial Flash Memory with 4Kbytes Uniform Sector

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EN25F05

BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size

of the area to be software protected against Program and Erase instructions.

SRP bit / OTP_LOCK bit The Status Register Protect (SRP) bit is operated in conjunction with the

Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal

allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the

Status Register (SRP, BP2, BP1, BP0) become read-only bits.

In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as

normal sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR

command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can

only be programmed once.

Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to

1, user must clear the protect bits before enter OTP mode and program the OTP code, then execute

WRSR command to lock the OTP sector before leaving OTP mode.

Write Protection

Applications that use non-volatile memory must take into consideration the possibility of noise and

other adverse system conditions that may compromise data integrity. To address this concern the

EN25F05 provides the following data protection mechanisms:

z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent

changes while the power supply is outside the operating specification.

z Program, Erase and Write Status Register instructions are checked that they consist of a

number of clock pulses that is a multiple of eight, before they are accepted for execution.

z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set

the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events:

â Power-up

â Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction

completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction

completion or Block Erase (BE) instruction completion or Chip Erase (CE) instruction

completion

z The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only.

This is the Software Protected Mode (SPM).

z The Write Protect (WP#) signal allows the Block Protect (BP2, BP1, BP0) bits and Status

z In addition to the low power consumption feature, the Deep Power-down mode offers extra

software protection from inadvertent Write, Program and Erase instructions, as all instructions

are ignored except one particular instruction (the Release from Deep Power-down instruction).

TABLE 3. Protected Area Sizes Sector Organization

Status Register

Content

BP2 BP1 BP0

Bit Bit Bit

Memory Content

Protect Blocks

Addresses

Density(KB)

Portion

All

000000h-00FFFFh 64KB

All

sector 0 to sector 14 000000h-00EFFFh 60KB

Lower 15/16

sector 0 to sector 13 000000h-00DFFFh 56KB

Lower 7/8

None

All

000000h-00FFFFh 64KB

All

PP, BE and SE is enabled without checking address; all sectors protected against Bulk

Erase

None

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. B, Issue Date: 2008/06/23

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