EN25F05 Datasheet, PDF(4/31 Page) Eon Silicon Solution Inc. – 512 Kbit Serial Flash Memory with 4Kbytes Uniform Sector

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EN25F05 Datasheet, PDF (4/31 Pages) Eon Silicon Solution Inc. – 512 Kbit Serial Flash Memory with 4Kbytes Uniform Sector

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EN25F05

MEMORY ORGANIZATION

The memory is organized as:

z 65,536 bytes

z Uniform Sector Architecture

2 blocks of 32-Kbyte

16 sectors of 4-Kbyte

z 256 pages (256 bytes each)

Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,

Block or Chip Erasable but not Page Erasable.

Table 2. Uniform Block Sector Architecture

Block

Sector

Address range

00F000h

00FFFFh

00E000h

00EFFFh

00D000h

00DFFFh

00C000h

00CFFFh

00B000h

00BFFFh

00A000h

00AFFFh

009000h

009FFFh

008000h

008FFFh

007000h

007FFFh

006000h

006FFFh

005000h

005FFFh

004000h

004FFFh

003000h

003FFFh

002000h

002FFFh

001000h

001FFFh

000000h

000FFFh

OPERATING FEATURES

SPI Modes

The EN25F05 is accessed through an SPI compatible bus consisting of four signals: Serial Clock

(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus

operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and

Mode 3, as shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus

master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal

is normally low. For Mode 3 the CLK signal is normally high. In either case data input on the DI pin is

sampled on the rising edge of the CLK. Data output on the DO pin is clocked out on the falling edge

of CLK.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. B, Issue Date: 2008/06/23

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