EN29GL128H Datasheet, PDF (18/54 Pages) Eon Silicon Solution Inc. – 128 Megabit (16384K x 8-bit / 8192K x 16-bit) Flash Memory Page mode Flash Memory, CMOS 3.0 Volt-only

EN29GL128H/L
The system may also write the Autoselect Command Sequence when the device is in Program
Suspend
mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not
stored in the memory array. When the device exits the Autoselect mode, the device reverts to Program
Suspend mode, and is ready for another valid operation.
After the Program Resume command is written, the device reverts to programming. The system can
determine the status of the program operation using the write operation status bits, just as in the
standard program operation.
The system must write the Program Resume command (address bits are “don't care”) to exit the
Program Suspend mode and continue the programming operation. Further writes of the Program
Resume command are ignored. Another Program Suspend command can be written after the device
has resumed programming.
Accelerated Program
Accelerated single word programming and write buffer programming operations are enabled through
the
WP#/ACC pin. This method is faster than the standard program command sequences.
If the system asserts V_HH on this input, the device automatically enters the Accelerated Program mode
and uses the higher voltage on the input to reduce the time required for program operations. The
system can then use the Write Buffer Load command sequence provided by the Accelerated Program
mode. Note that if a “Write-to-Buffer-Abort Reset” is required while in Accelerated Program mode, the
full 3-cycle RESET command sequence must be used to reset the device. Removing V_HH from the ACC
input, upon completion of the embedded program operation, returns the device to normal operation.
• Sectors must be unlocked prior to raising WP#/ACC to V_HH.
• The WP#/ACC pin must not be at V_HH for operations other than accelerated programming, or device
damage may result.
• It is recommended that WP#/ACC apply V_HH after power-up sequence is completed. In addition, it is
recommended that WP#/ACC apply from V_HH to VIH/VIL before powering down V_CC/ V_IO .
Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The following
subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase
algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid
after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is
valid only for the last word being programmed in the write-buffer-page during Write Buffer Programming.
Reading Data# Polling status on any word other than the last word to be programmed in the write-
buffer-page returns false status information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The
system must provide the program address to read valid status information on DQ7. If a program
address falls within a protected sector, Data# polling on DQ7 is active, then that sector returns to the
read mode.
During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Embedded
Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a
“1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read
valid status information on DQ7.
This Data Sheet may be revised by subsequent versions
18
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. H, Issue Date: 2009/10/01
www.eonssi.com