EN25QH64 Datasheet, PDF(14/65 Page) Eon Silicon Solution Inc. – 64 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

EN25QH64 Datasheet, PDF (14/65 Pages) Eon Silicon Solution Inc. – 64 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

◁

Table 3. Protected Area Sizes Sector Organization

EN25QH64

Status Register Content

Memory Content

BP3 BP2 BP1 BP0

Bit Bit Bit Bit

Protect Areas

Addresses

Density(KB) Portion

None

Block 127

7F0000h-7FFFFFh 64KB

Upper 1/128

Block 126 to 127 7E0000h-7FFFFFh 128KB

Upper 2/128

Block 124 to 127 7C0000h-7FFFFFh 256KB

Upper 4/128

Block 120 to 127 780000h-7FFFFFh 512KB

Upper 8/128

Block 112 to 127 700000h-7FFFFFh 1024KB

Upper 16/128

Block 96 to 127 600000h-7FFFFFh 2048KB

Upper 32/128

All

000000h-7FFFFFh 8192KB

All

None

Block 0

000000h-00FFFFh 64KB

Lower 1/128

Block 0 to 1

000000h-01FFFFh 128KB

Lower 2/128

Block 0 to 3

000000h-03FFFFh 256KB

Lower 4/128

Block 0 to 7

000000h-07FFFFh 512KB

Lower 8/128

Block 0 to 15

000000h-0FFFFFh 1024KB

Lower 16/128

Block 0 to 31

000000h-1FFFFFh 2048KB

Lower 32/128

All

000000h-7FFFFFh 8192KB

All

INSTRUCTIONS

All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial

Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is

driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,

on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).

The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction

code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by

both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has

been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed

(Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output

FAST_READ (EBh), Read Status Register (RDSR), Read Information Register (RDIFR) or Release

from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is

followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out

sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write

Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)

instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction

is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock

pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at

any time the input byte is not a full byte, nothing will happen and WEL will not be reset.

In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down

(RES ) minimum number of bytes specified has to be given, without which, the command will be

ignored.

In the case of Page Program, if the number of byte after the command is less than 4 (at least 1

data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any

less or more will cause the command to be ignored.

All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase

cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues

unaffected.

This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

Rev. J, Issue Date: 2013/12/27

www.eonssi.com

▷