EN25Q128 Datasheet, PDF (14/57 Pages) Eon Silicon Solution Inc. – 128 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

Table 3. Protected Area Sizes Sector Organization
EN25Q128
Status Register Content
Memory Content
BP3 BP2
Bit Bit
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
BP1
Bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
Bit
Protect Areas
Addresses
0
None
None
1
Block 0 to 254 000000h-FEFFFFh
0
Block 0 to 253 000000h-FDFFFFh
1
Block 0 to 251 000000h-FBFFFFh
0
Block 0 to 247 000000h-F7FFFFh
1
Block 0 to 239 000000h-EFFFFFh
0
Block 0 to 223 000000h-DFFFFFh
1
All
000000h-FFFFFFh
0
None
None
1
Block 255 to 1 FFFFFFh-010000h
0
Block 255 to 2 FFFFFFh-020000h
1
Block 255 to 4 FFFFFFh-040000h
0
Block 255 to 8 FFFFFFh-080000h
1
Block 255 to 16 FFFFFFh-100000h
0
Block 255 to 32 FFFFFFh-200000h
1
All
FFFFFFh-000000h
Density(KB) Portion
None
16320KB
16256KB
16128KB
15872KB
15360KB
14336KB
16384KB
None
16320KB
16256KB
16128KB
15872KB
15360KB
14336KB
16384KB
None
Lower 255/256
Lower 254/256
Lower 252/256
Lower 248/256
Lower 240/256
Lower 224/256
All
None
Upper 255/256
Upper 254/256
Upper 252/256
Upper 248/256
Upper 240/256
Upper 224/256
All
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is
driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has
been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output
FAST_READ (EBh), Read Status Register (RDSR) or Release from Deep Power-down, and Read
Device ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence.
Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write
Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction
is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock
pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at
any time the input byte is not a full byte, nothing will happen and WEL will not be reset.
In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down
(RES ) minimum number of bytes specified has to be given, without which, the command will be
ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1
data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any
less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.
This Data Sheet may be revised by subsequent versions
14
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2011/09/19
www.eonssi.com