EN25QH32 Datasheet, PDF (12/63 Pages) Eon Silicon Solution Inc. – 32 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

Table 3. Protected Area Sizes Sector Organization
EN25QH32
Status Register Content
Memory Content
BP3 BP2
Bit Bit
00
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
BP1
Bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
Bit
Protect Areas
Addresses
0
None
None
1
Block 63
3F0000h-3FFFFFh
0
Block 62 to 63 3E0000h-3FFFFFh
1
Block 60 to 63 3C0000h-3FFFFFh
0
Block 56 to 63 380000h-3FFFFFh
1
Block 48 to 63 300000h-3FFFFFh
0
Block 32 to 63 200000h-3FFFFFh
1
All
000000h-3FFFFFh
0
None
None
1
Block 0
000000h-00FFFFh
0
Block 0 to 1
000000h-01FFFFh
1
Block 0 to 3
000000h-03FFFFh
0
Block 0 to 7
000000h-07FFFFh
1
Block 0 to 15 000000h-0FFFFFh
0
Block 0 to 31 000000h-1FFFFFh
1
All
000000h-3FFFFFh
Density(KB) Portion
None
64KB
128KB
256KB
512KB
1024KB
2048KB
4096KB
None
64KB
128KB
256KB
512KB
1024KB
2048KB
4096KB
None
Upper 1/64
Upper 2/64
Upper 4/64
Upper 8/64
Upper 16/64
Upper 32/64
All
None
Lower 1/64
Lower 2/64
Lower 4/64
Lower 8/64
Lower 16/64
Lower 32/64
All
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is
driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has
been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output
FAST_READ (EBh), Read Status Register (RDSR), Read Information Register (RDIFR) or Release
from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is
followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out
sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write
Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction
is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock
pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at
any time the input byte is not a full byte, nothing will happen and WEL will not be reset.
In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down
(RES ) minimum number of bytes specified has to be given, without which, the command will be
ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1
data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any
less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.
This Data Sheet may be revised by subsequent versions
12
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2012/01/30
www.eonssi.com