EN25S32 Datasheet, PDF (11/59 Pages) Eon Silicon Solution Inc. – 32 Megabit 1.8V Serial Flash Memory with 4Kbyte Uniform Sector

Table 3. Protected Area Sizes Sector Organization
EN25S32
Status Register Content
Memory Content
BP3 BP2
Bit Bit
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
BP1
Bit
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BP0
Bit
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Protect Areas
Addresses
Density(KB) Portion
None
Block 0 to 62
Block 0 to 61
Block 0 to 59
Block 0 to 55
Block 0 to 47
Block 0 to 31
All
None
Block 63 to 1
Block 63 to 2
Block 63 to 4
Block 63 to 8
Block 63 to 16
Block 63 to 32
All
None
000000h-3EFFFFh
000000h-3DFFFFh
000000h-3BFFFFh
000000h-37FFFFh
000000h-2FFFFFh
000000h-1FFFFFh
000000h-3FFFFFh
None
3FFFFFh-010000h
3FFFFFh-020000h
3FFFFFh-040000h
3FFFFFh-080000h
3FFFFFh-100000h
3FFFFFh-200000h
000000h-3FFFFFh
None
4032KB
3968KB
3840KB
3584KB
3072KB
2048KB
4096KB
None
4032KB
3968KB
3840KB
3584KB
3072KB
2048KB
4096KB
None
Lower 63/64
Lower 62/64
Lower 60/64
Lower 56/64
Lower 48/64
Lower 32/64
All
None
Upper 63/64
Upper 62/64
Upper 60/64
Upper 56/64
Upper 48/64
Upper 32/64
All
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial
Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is
driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first,
on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).
The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by
both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has
been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed
(Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output
FAST_READ (EBh), Read Status Register (RDSR), Read Suspend Status Register (RDSSR) or
Release from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction se-
quence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write
Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction
is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock
pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at
any time the input byte is not a full byte, nothing will happen and WEL will not be reset.
In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down
(RES ) minimum number of bytes specified has to be given, without which, the command will be
ignored.
In the case of Page Program, if the number of byte after the command is less than 4 (at least 1
data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any
less or more will cause the command to be ignored.
All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase
cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues
unaffected.
This Data Sheet may be revised by subsequent versions
11
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc.,
Rev. J, Issue Date: 2012/01/19
www.eonssi.com