EN25Q80B Datasheet, PDF (10/64 Pages) Eon Silicon Solution Inc. – 8 Megabit Serial Flash Memory with 4Kbyte Uniform Sector

EN25Q80B
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to 1,
user must clear the protect bits before entering OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the
EN25Q80B provides the following data protection mechanisms:
z Power-On Reset and an internal timer (tPUW) can provide protection against inadvertent changes
while the power supply is outside the operating specification.
z Program, Erase and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set
the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction
completion or Page Program (PP) instruction completion or Sector Erase (SE) instruction
completion or Half Block Erase (HBE) / Block Erase (BE) instruction completion or Chip Erase
(CE) instruction completion
z The Block Protect (BP3, BP2, BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
z The Write Protect (WP#) signal allows the Block Protect (BP3, BP2, BP1, BP0) bits and Status
Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).
z In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions are
ignored except one particular instruction (the Release from Deep Power-down instruction).
Table 3. Protected Area Sizes Sector Organization
Status Register Content
Memory Content
BP3 BP2 BP1 BP0
Bit Bit Bit Bit
Protect Areas
0
0
0
0
None
0
0
0
1
Sector 0 to 253
0
0
1
0
Sector 0 to 251
0
0
1
1
Sector 0 to 247
0
1
0
0
Sector 0 to 239
0
1
0
1
Sector 0 to 223
0
1
1
0
Sector 0 to 191
0
1
1
1
All
1
0
0
0
None
1
0
0
1
Sector 0 to 1
1
0
1
0
Sector 0 to 3
1
0
1
1
Sector 0 to 7
1
1
0
0
Sector 0 to 15
1
1
0
1
Sector 0 to 31
1
1
1
0
Sector 0 to 63
1
1
1
1
All
Addresses
Density(KB) Portion
None
000000h-0FDFFFh
000000h-0FBFFFh
000000h-0F7FFFh
000000h-0EFFFFh
000000h-0DFFFFh
000000h-0BFFFFh
000000h-0FFFFFh
None
000000h-001FFFh
000000h-003FFFh
000000h-007FFFh
000000h-00FFFFh
000000h-01FFFFh
000000h-03FFFFh
000000h-0FFFFFh
None
1016KB
1008KB
992KB
960KB
896KB
768KB
1024KB
None
8KB
16KB
32KB
64KB
128KB
256KB
1024KB
None
Lower 254/256
Lower 252/256
Lower 248/256
Lower 240/256
Lower 224/256
Lower 192/256
All
None
Lower 2/256
Lower 4/256
Lower 8/256
Lower 16/256
Lower 32/256
Lower 64/256
All
Note:
If any sub-block regions are protected, BE/HBE at that block/half block is disabled.
e.g. Disable BE at last block if BP [3:0] = 0001, 0010, 0011
Disable HBE at last half block if BP [3:0] = 0001, 0010
Disable BE at first block if BP [3:0] =1001, 1010, 1011, 1100
Disable HBE at first half block if BP [3:0] =1001, 1010, 1011
This Data Sheet may be revised by subsequent versions
10
or modifications due to changes in technical specifications.
©2013 Eon Silicon Solution, Inc.,
Rev. B, Issue Date: 2013/10/16
www.eonssi.com