EN2360QI Datasheet, PDF (3/24 Pages) Enpirion, Inc. – 6A Voltage Mode Synchronous Buck PWM DC-DC Converter with Integrated Inductor

PIN
16-24
27-28,
61-63
29-34
35-41
42
43
44
45
46
47
48
49
50
51
52, 53
54
55
56
57
58
60
69
EN2360QI
NAME I/O
FUNCTION
VOUT
O
Regulated converter output. Connect these pins to the load and place output capacitor
between these pins and PGND pins 29-31.
NO CONNECT – These pins are internally connected to the common switching node of the
NC(SW) NC internal MOSFETs. They are not to be electrically connected to any external signal, ground,
or voltage. Failure to follow this guideline may result in damage to the device.
PGND
G
Input/Output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT and PVIN pin descriptions for more details.
PVIN
P
Input power supply. Connect to input power supply. Decouple with input capacitor to
PGND pins 32-34.
Internal 3.3V linear regulator output. Connect this pin to AVIN (Pin 51) for applications
AVINO O where operation from a single input voltage (PVIN) is required. If AVINO is being used,
place a 1µF, X5R, capacitor between AVINO and AGND as close as possible to AVINO.
PG I/O Place a 47nF, X5R, capacitor between this pin and BTMP.
BTMP I/O See pin 43 description.
VDDB
O
Internal regulated voltage used for the internal control circuitry. Place a 0.22µF, X5R,
capacitor between this pin and BGND.
BGND G See pin 45 description.
S_IN
I
Digital Input. This pin accepts either an input clock to phase lock the internal switching
frequency or a S_OUT signal from another EN2360QI. Leave this pin floating if not used.
S_OUT O Digital Output. PWM signal is output on this pin. Leave this pin floating if not used.
Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used for power
POK O system state indication. POK is logic high when VOUT is within -10% of VOUT nominal.
Leave this pin floating if not used.
ENABLE
I
Input Enable. Applying a logic high to this pin enables the output and initiates a soft-start.
Applying a logic Low disables the output. Do not leave floating.
AVIN
P
3.3V Input power supply for the controller. Place a 0.1µF, X5R, capacitor between AVIN
and AGND.
AGND
G
Analog Ground. This is the ground return for the controller. All AGND pins need to be
connected to a quiet ground.
External Feedback Input. The feedback loop is closed through this pin. A voltage divider at
VFB I/O VOUT is used to set the output voltage. The mid-point of the divider is connected to VFB. A
phase lead capacitor from this pin to VOUT is also required to stabilize the loop.
EAIN
O
Optional Error Amplifier Input. Allows for customization of the control loop for performance
optimization. Leave this pin floating if not used.
Soft-start node. The soft-start capacitor is connected between this pin and AGND. The
SS I/O value of this capacitor determines the startup time. See Soft-Start Operation in the
Functional Description section for details.
Programmable over-current protection. Placement of a resistor on this pin will adjust the
RCLX
I/O
over-current protection threshold. See Table 2 for the recommended RCLX Value to set
OCP at the nominal value specified in the Electrical Characteristics table. No current limit
protection when this pin is left floating.
FADJ
Adding a resistor (R_FS) to this pin will adjust the switching frequency of the EN2360QI. See
I/O Table 1 for suggested resistor values on R_FS for various PVIN/VOUT combinations to
maximize efficiency. Do not leave this pin floating.
CGND
Test pin. For Enpirion Internal Use Only. Connect to GND plane at all times.
PGND
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-
sinking purposes.
©Enpirion 2012 all rights reserved, E&OE
07514
Enpirion Confidential
September 17, 2012
www.enpirion.com, Page 3
Rev: A