EN2360QI Datasheet, PDF (15/24 Pages) Enpirion, Inc. – 6A Voltage Mode Synchronous Buck PWM DC-DC Converter with Integrated Inductor

1.800
Rfs vs. SW Frequency
1.600
1.400
1.200
1.000
0.800
CONDITIONS
V_IN = 6V to 12V
V_OUT = 0.8V to 3.3V
0.600
0 2 4 6 8 10 12 14 16 18 20 22
R_FS RESISTOR VALUE (kΩ)
Figure 7. R_FS versus Switching Frequency
The efficiency performance of the EN2360QI for
various VOUTs can be optimized by adjusting the
switching frequency. Table 1 shows recommended
R_FS values for various VOUTs in order to optimize
performance of the EN2360QI.
PVIN
12V
VOUT
1.0V
1.2V
1.8V
2.5V
3.3V
5.0V
R_FS
3k
3.3k
4.87k
10k
15k
22k
Table 1: Recommended R_FS Values
Spread Spectrum Mode
The external clock frequency may be swept
between 0.8MHz and 1.6MHz at repetition rates of
up to 10 kHz in order to reduce EMI frequency
components.
Soft-Start Operation
Soft start is a means to ramp the output voltage
gradually upon start-up. The output voltage rise
time is controlled by the choice of soft-start
capacitor, which is placed between the SS pin (pin
56) and the AGND pin (pin 52).
Rise Time (ms): T_R ≈ C_ss [nF] x 0.06
During start-up of the converter, the reference
voltage to the error amplifier is linearly increased to
its final level by an internal current source of
approximately 10µA. Typical soft-start rise time is
~2.8ms with SS capacitor value of 47nF. The rise
time is measured from when V_IN > V_UVLOR and
ENABLE pin voltage crosses its logic high
EN2360QI
threshold to when V_OUT reaches its programmed
value.
POK Operation
The POK signal is an open drain signal (requires a
pull up resistor to AVIN or similar voltage) from the
converter indicating the output voltage is within the
specified range. Typically, a 100kΩ or lower
resistance is used as the pull-up resistor. The POK
signal will be logic high (AVIN) when the output
voltage is above 90% of the programmed voltage
level. If the output voltage is below this point, the
POK signal will be a logic low. The POK signal can
be used to sequence down-stream converters by
tying to their enable pins.
Over-Current Protection (OCP)
The current limit function is achieved by sensing
the current flowing through a sense PFET. When
the sensed current exceeds the current limit, both
power FETs are turned off for the rest of the
switching cycle. If the over-current condition is
removed, the over-current protection circuit will re-
enable PWM operation. If the over-current condition
persists, the circuit will continue to protect the load.
The OCP trip point is nominally set as specified in
the Electrical Characteristics table. In the event the
OCP circuit trips consistently in normal operation,
the device enters a hiccup mode. While in hiccup
mode, the device is disabled for a short while and
restarted with a normal soft-start. The hiccup time
is approximately 32ms. This cycle can continue
indefinitely as long as the over current condition
persists.
The OCP trip point can be programmed to trip at a
lower level via the RCLX pin. The value of the
resistor connected between RCLX and ground will
determine the OCP trip point. Generally, the higher
the RCLX value, the higher the current limit
threshold. Note that if RCLX pin is left open the
output current will be unlimited and the device will
not have current limit protection. Reference Table 2
for a list of recommended resistor values on RCLX
that will set the OCP trip point at the typical value of
9A, also specified in the Electrical Characteristics
table.
V_OUT Range
0.6V < V_OUT ≤ 0.9V
0.9V < V_OUT ≤ 1.2V
1.2V < V_OUT ≤ 2.0V
2.0V < V_OUT ≤ 5.0V
R_CLX Value
36.5k
38.4k
40.2k
45.3k
Table 2: Recommended R_CLX Values vs. V_OUT
©Enpirion 2012 all rights reserved, E&OE
07514
Enpirion Confidential
September 17, 2012
www.enpirion.com, Page 15
Rev: A