EN2360QI Datasheet, PDF (14/24 Pages) Enpirion, Inc. – 6A Voltage Mode Synchronous Buck PWM DC-DC Converter with Integrated Inductor

Power Power Up Sequence
The EN2360QI is designed to be powered by either
a single input supply (PVIN) or two separate
supplies: one for PVIN and the other for AVIN.
Single Input Supply Application (PVIN):
47nF
0.22µF
V_IN
22 F
1206
RVB
4.75k
F
PG BTMP VDDB BGND
PVIN
VOUT
EN2360QI
ENABLE
AVINO
AVIN
F
SS
VFB
47nF
PGND
FADJ
AGND
PGND
RCLX
V_OUT
2x
F R_A
CA
0805
RCA
RB
RFS
RCLX
Figure 5. Single Supply Applications Circuit
The EN2360QI has an internal linear regulator that
converts PVIN to 3.3V. The output of the linear
regulator is provided on the AVINO pin once the
device is enabled. AVINO should be connected to
AVIN on the EN2360QI. In this application, the
following external components are required: Place
a 1µF, X5R/X7R, capacitor between AVINO and
AGND as close as possible to AVINO. Place a
0.1µF, X5R/X7R, capacitor between AVIN and
AGND as close as possible to AVIN. In addition,
place a resistor (R_VB) between VDDB and AVIN, as
shown in Figure 5. Enpirion recommends
R_VB=4.75kΩ. In this application, ENABLE cannot be
asserted before PVIN. If no external enable signal
is used, tying ENABLE to AVIN meets this
requirement.
Dual Input Supply Application (PVIN and AVIN):
Figure 6: Dual Input Supply Application Circuit
EN2360QI
In this application, place a 0.1µF, X7R, capacitor
between AVIN and AGND as close as possible to
AVIN. Refer to Figure 6 for a recommended
schematic for a dual input supply application.
For dual input supply applications, the sequencing
of the two input supplies, PVIN and AVIN, is very
important. There are two common acceptable turn-
on sequences for the device. AVIN can always
come up before PVIN. If PVIN comes up before
AVIN, then ENABLE should be toggled last, after
AVIN is asserted. During turn-off, the ENABLE
should be toggled low before AVIN or PVIN is
disabled.
Enable Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted (high)
the device will undergo a normal soft-start, allowing
the output voltage to rise monotonically into
regulation. A logic low will disable the converter and
the device will power down in a controlled manner.
The ENABLE signal has to be low for at least the
ENABLE Lockout Time (8ms) in order for the
device to be re-enabled.
Pre-Bias Precaution
The EN2360QI is not designed to be turned on into
a pre-biased output voltage. Be sure the output
capacitors are not charged or the output of the
EN2360QI is not pre-biased when the EN2360QI is
first enabled.
Frequency Synchronization
The switching frequency of the EN2360QI can be
phase-locked to an external clock source to move
unwanted beat frequencies out of band. The
internal switching clock of the EN2360QI can be
phase locked to a clock signal applied to the S_IN
pin. An activity detector recognizes the presence of
an external clock signal and automatically phase-
locks the internal oscillator to this external clock.
Phase-lock will occur as long as the input clock
frequency is in the range of 0.8MHz to 1.6MHz.
When no clock is present, the device reverts to the
free running frequency of the internal oscillator.
Adding a resistor (R_FS) to the FADJ pin will adjust
the switching frequency. If a 3kΩ resistor is placed
on FADJ the nominal switching frequency of the
EN2360QI is 1MHz. Figure 7 shows the typical R_FS
resistor value versus switching frequency.
©Enpirion 2012 all rights reserved, E&OE
07514
Enpirion Confidential
September 17, 2012
www.enpirion.com, Page 14
Rev: A