EM6635 Datasheet, PDF (22/39 Pages) EM Microelectronic - MARIN SA – Low Power Microcontroller with RC and 32kHz oscillators and 9 high drive outputs

EM6635
10. Timer 2
The timer 2 can operate in two modes: The Zero Stop Mode as explained in timer1 description and the Auto Reload Mode.
The clock frequency can be selected by "SelT2F2" and "SelT2F1" control bits in "Timer2 Ctl" at address H59:
SelT2F2
0
0
1
1
SelT2F1
0
1
0
1
Timer 2 Clock Frequency
4 Hz
16 Hz
64 Hz
256 Hz
The timer 2 has the same general structure as timer 1, see description there.
10.1 Zero Stop Mode
The operation in this mode is the same as for timer 1, only the CPU access address is H5A for "Timer2 Hi-Data", H5B for
"Timer2 Low-Data" and H59 for "Timer2 Ctl".
10.2 Auto Reload Mode
This mode of timer2 is enabled, if the "ARMode", bit2 of "Timer2 Ctl", address H59 is set to "1".
The timer starts counting down, when a non-zero data is loaded into its 2 reload registers (address H5A, "Timer2 Hi-Data"
and address H5B, "Timer2 Low-Data"). When the counter has arrived at zero state, a "Timer2" interrupt is generated (bit 3,
address H64).
The counter is then automatically reload with the data stored in the reload register (previously written there by the CPU),
and starts again to count down.
This sequence is repeated until the Auto Reload Mode is stopped by setting the "ARMode" bit to "0". The Auto Reload
Mode is only hold by writing "0000" into the "Timer2 Hi-Data" and "Timer2 Low-Data" reload registers.
The timer 2 period in the Auto Reload Mode is the same as defined for timer1 in Auto Reload Mode, see there.
If an all-zero data is written into the 2 reload registers, no interrupt will be generated and the timer 2 remains at this state
until a non-zero data is written into the 2 reload registers. Then, the described sequence starts again.
CPU Write
AR Mode
Timer Clock
Timer
Counter
Timer
Interrupt
Ctl
Hi
Low
0
3
2
1
0
3
Fig.13: Timer 2 Timing in Auto Reload Mode
2
1
0
3
CPU Access Format:
Register
Timer2 Ctl
Timer2 Hi-Data
Timer2 Low-Data
Add Hex Add Dec
59
89
W
R
5A
90
W
R
5B
91
W
R
bit3
x
0
MSB
MSB
bit2
ARMode
ARMode
(hi nibble)
(low nibble)
bit1
SelT2F2
SelT2F2
bit0
SelT2F1
SelT2F1
LSB
LSB
Copyright  2002, EM Microelectronic-Marin SA
22
03/03 REV. B
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