EM6635 Datasheet, PDF (10/39 Pages) EM Microelectronic - MARIN SA – Low Power Microcontroller with RC and 32kHz oscillators and 9 high drive outputs

EM6635
7. Prescaler
The prescaler is a 15 stages divider chain, which delivers clock signals for the peripheral circuits such as timer, frequency
generator, debouncer, etc. The input is the 32768Hz system clock from Quartz Oscillator or external clock.
Note: if external clock is applied it should be also 32768Hz to keep timing specified in this specification, in other case all
timing change relative to external clock compared to 32768Hz.
The system reset initialises the prescaler to all 0, except the 1s stage, which is set to 1.
The prescaler generates four interrupt requests: INT-TB1, INT-TB2, INT-TB3, INT-TB4.
The source is selected by Sel/INT8.
Interrupt
TB1
TB2
TB3
TB4
Sel/INT8
0
1
1Hz
1Hz
64Hz
8Hz
32Hz
16Hz
128Hz
64Hz
Both interrupts appear at the positive edge of the corresponding signal.
The first INT_TB1 occurs 1 sec after the end of the system reset.
The prescaler can be reset partially from 32Hz to 1Hz by writing "1" to "ResetCK" of HW-Ctl-2 (bit 0 at address H43). A read
access to that bit gives always "0".
Note: this prescaler reset shortens the watchdog time out tWD.
The prescaler creates a clock signal for the clocked pull down at inputs, e.g. at port P1. This is a 512Hz signal with an
active time of 31µs if OP-6A is chosen or 64µs at OP-6B.
7.1 Time Base Capture
The state of the prescaler stages 128Hz to 16Hz and 8Hz to 1Hz can be read by the CPU by a read access to address H55
(a write has no effect). The range selection is done by bit 3 of HW-Ctl-2, address H42 or H43. A "1" at this "SelTBCapHi"
selects the range from 128Hz to 16Hz for read.
This time base capture capability is mostly designed for 4 bits application. The corresponding data are directly read from the
prescaler. If two consecutive capture accesses are made to read the two ranges, the resulting data representation (8 bits)
may not be coherent, due to a possible prescaler update event occuring to the 128 Hz stage plus its correlated carry to the
following stages.
8. EM6635 Input / Output Ports
8.1 Input Port P1
The port P1 is a 4bits input port used to read the terminal logic levels P10 to P13 into the CPU.
The port is equipped with 4 debouncers, which can be enabled by signal "P1DebOn", commonly for all 4 bits. With
debouncers active, any input level must be present glitch free for at least the debounce time tDEB=1.95ms, to be
transferred to the debouncer output, which can be read by the CPU.
When "P1DebOn" is at "0" level, the port P1 inputs are directly passed to the debouncer outputs.
Debouncer
Clock 512Hz
Reset System
DEBOUNCER function (signal must be stable during two Deb Clk rising edges)
1
1
1
2
1
2
1
2
glitch between two clocks
Fig.8: Debouncer function
1
2
Copyright  2002, EM Microelectronic-Marin SA
10
03/03 REV. B
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