EMP116MFAW Datasheet, PDF (7/11 Pages) Emerging Memory & Logic Solutions Inc – 1Mx16 Pseudo Static RAM

TIMING DIAGRAMS
Preliminary
EMP116MFAW Series
1Mx16 Pseudo Static RAM
READ CYCLE (1) (Address controlled, CS#=OE#=V_IL, ZZ#=WE#=V_IH, UB# or/and LB#=V_IL)
t_RC
Address
t_OH ^tAA
Data Out
Previous Data Valid
Data Valid
READ CYCLE (2) (ZZ#=WE#=V_IH)
Address
CS#
LB#, UB#
OE#
Data Out
High-Z
t_RC
t_{AA tCO}
t_BA
t_OE
t_OLZ
t_BLZ
t_LZ
Data Vaild
t_OH
t_HZ
t_BHZ
t_OHZ
NOTES (READ CYCLE)
1. t_HZ , t_BHZ and t_OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. Do not Access device with cycle timing shorter than t_RC for continuous periods > 1us.
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Rev 0.0