HB52R649E1U-A6B Datasheet, PDF (8/20 Pages) Elpida Memory – 512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC100 SDRAM

HB52R649E1U-A6B/B6B
Block Diagram
RS0
RDQMB0
4 N0
DQ0 to DQ3
4 N1
DQ4 to DQ7
RDQMB1
4 N2
DQ8 to DQ11
4 N3
DQ12 to DQ15
4 N4
CB0 to CB3
RDQMB4
DQMB CS
DQMB CS
D0
I/O0
to I/O3
DQ32 to DQ35
4
N9
D9
I/O0
to I/O3
DQMB CS
DQMB CS
D1
I/O0
to I/O3
DQ36 to DQ39
4
N10
D10
I/O0
to I/O3
RDQMB5
DQMB CS
DQMB CS
D2
I/O0
to I/O3
DQ40 to DQ43
4
N11
D11
I/O0
to I/O3
DQMB CS
DQMB CS
D3
I/O0
to I/O3
DQ44 to DQ47
4
N12
D12
I/O0
to I/O3
DQMB CS
D4
I/O0
to I/O3
DQMB CS
D13
4
CB4 to CB7
N13
I/O0
to I/O3
RS2
RDQMB2
4 N5
DQ16 to DQ19
4 N6
DQ20 to DQ23
RDQMB6
DQMB CS
DQMB CS
D5
I/O0
to I/O3
DQ48 to DQ51
4
N14
D14
I/O0
to I/O3
DQMB CS
DQMB CS
D6
D15
I/O0
to I/O3
4
DQ52 to DQ55
N15
I/O0
to I/O3
RDQMB3
4 N7
DQ24 to DQ27
4 N8
DQ28 to DQ31
RDQMB7
DQMB CS
DQMB CS
D7
I/O0
to I/O3
DQ56 to DQ59
4
N16
D16
I/O0
to I/O3
DQMB CS
DQMB CS
D8
I/O0
to I/O3
DQ60 to DQ63
4
N17
D17
I/O0
to I/O3
S0, S2
R
DQMB0 to DQMB7
E
BA0 to BA1
G
A0 to A12
I
RE
S
CE
T
CKE0
E
W
R
V_CC
RS0, RS2
RDQMB0 to RDQMB7
RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D17
RA0 to RA12 -> A0 to A12: SDRAMs D0 to D17
RRAS -> RAS: SDRAMs D0 to D17
CCAS -> CAS: SDRAMs D0 to D17
RCKE0 -> CKE: SDRAMs D0 to D17
RW -> WE: SDRAMs D0 to D17
R101
REGE
PLL CK
CK0
CK1 to CK3
V_CC
C0 to C18
V_SS
R200
PLL
R201 to R203
V_SS
C100 to C102
V_CC (D0 to D17, U0)
C19 to C44 C200 to C201
V_SS (D0 to D17, U0)
Serial PD
SCL
SCL
SDA
SDA
U0
WP
A0 A1 A2
R100
SA0 SA1 SA2 VSS
Notes:
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
* D0 to D17: HM5225405
PLL: 2510
Register: 162834
U0: EEPROM
C0 to C18: 0.22 µF
C19 to C44: 2200 pF
C100 to C102: 10pF
R200 to R203: 10 Ω
R100: 47 kΩ
R101: 10 kΩ
C200 to C201: 2.2 µF
N0 to N17: Network registor 10 Ω
Preliminary Data Sheet E0022H10
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