HB52R649E1U-A6B Datasheet, PDF (15/20 Pages) Elpida Memory – 512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC100 SDRAM

HB52R649E1U-A6B/B6B
Capacitance (Ta = 25°C, V_CC = 3.3 V ± 0.3 V)
Parameter
Symbol
Max
Unit
Notes
Input capacitance (Address)
C_I1
15
pF
1, 2, 4
Input capacitance (RE, CE, W)
C_I2
15
pF
1, 2, 4
Input capacitance (CKE)
C_I3
23
pF
1, 2, 4
Input capacitance (S)
C_I4
15
pF
1, 2, 4
Input capacitance (CK)
C_I5
40
pF
1, 2, 4
Input capacitance (DQMB)
C_I6
15
pF
1, 2, 4
Input/Output capacitance (DQ)
C_I/O1
15
pF
1, 2, 3, 4
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
3. DQMB = V_IH to disable Data-out.
4. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 55°C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V)
Parameter
System clock cycle time
(CE latency = 3)
(CE latency = 4)
CK high pulse width
CK low pulse width
Access time from CK
(CE latency = 3)
(CE latency = 4)
Data-out hold time
CK to Data-out low impedance
CK to Data-out high impedance
Data-in setup time
Data in hold time
Address setup time
Address hold time
CKE setup time
CKE setup time for power down exit
CKE hold time
Symbol
t _CK
PC100
Symbol
Tclk
HB52R649E1U
-A6B/B6B
Min
Max
10
—
t _CK
Tclk
10
—
t _CKH
Tch
4
—
t _CKL
Tcl
4
—
t _AC
Tac
—
6.9
t _AC
Tac
—
6.9
t _OH
Toh
2.1
—
t _LZ
1.1
—
t _HZ
—
6.9
t _DS
Tsi
2.9
—
t _DH
Thi
1.9
—
t _AS
Tsi
2.6
—
t _AH
Thi
1.6
—
t _CES
Tsi
2.6
—
t _CESP
Tpde
2.6
—
t _CEH
Thi
1.6
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
1
1, 2
1, 2
1, 2, 3
1, 4
1
1
1
1, 5
1, 5
1
1
Preliminary Data Sheet E0022H10
15