MC-4R64CPE6C Datasheet, PDF (5/16 Pages) NEC – Direct Rambus DRAM RIMM Module 64M-BYTE 32M-WORD x 16-BIT

MC-4R64CPE6C
Module Connector Pad Description
(1/2)
Signal
I/O
Type
Description
GND
–
–
Ground reference for RDRAM core and interface. 72 PCB connector pads.
LCFM
I
RSL
LCFMN
I
RSL
LCMD
I
VCMOS
LCOL4..LCOL0
I
RSL
E_LCTM
I
RSL
LCTMN
I
RSL
O_LDQA8..LDQA0
I/O
RSL
L ^LDQB8..LDQB0
I/O
RSL
LROW2..LROW0
I
LSCK
I
RSL
VCMOS
NC
–
–
RCFM
RCFMN
I
RSL
I
RSL
RCMD
I
RCOL4..RCOL0
I
VCMOS
RSL
RCTM
I
RSL
RCTMN
I
RSL
RDQA8..RDQA0 I/O
RSL
RDQB8..RDQB0 I/O
RSL
RROW2..RROW0 I
RSL
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
Serial Command used to read from and write to the control registers. Also used
for power management.
Column bus. 5-bit bus containing control and address information for column
accesses.
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Positive polarity.
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQA8 is non-functional on modules with x16 RDRAM devices.
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
and the RDRAM. LDQB8 is non-functional on modules with x16 RDRAM devices.
Row bus. 3-bit bus containing control and address information for row accesses.
Serial clock input. Clock source used to read from and write to the RDRAM
control registers.
These pads are not connected. These 24 connector pads are reserved for future
P_use.
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
r^{Clock from master. Interface clock used for receiving RSL signals from the}
Channel. Negative polarity.
Serial Command Input used to read from and write to the control registers. Also
o _{used for power management.}
Column bus. 5-bit bus containing control and address information for column
accesses.
d Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Positive polarity.
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
u _{Data bus A. A 9-bit bus carrying a byte of read or write data between the Channel}
and the RDRAM. RDQA8 is non-functional on modules with x16 RDRAM devices.
Data bus B. A 9-bit bus carrying a byte of read or write data between the Channel
c ^{and the RDRAM. RDQB8 is non-functional on modules with x16 RDRAM devices.}
t ^{Row bus. 3-bit bus containing control and address information for row accesses.}
Preliminary Data Sheet E0051N11
5