HB54R1G9F2-B75B Datasheet, PDF (5/16 Pages) Elpida Memory – 1GB Registered DDR SDRAM DIMM

HB54R1G9F2-B75B/10B
Serial PD Matrix*¹
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08
128
256 byte
2
Memory type
0
3
Number of row address
0
4
Number of column address
0
5
Number of DIMM ranks
0
6
Module data width
0
E7
Module data width continuation
0
8
Voltage interface level of this assembly 0
9
DDR SDRAM cycle time, CL = X
-B75B
0
O^-10B
1
10
SDRAM access from clock (tAC)
-B75B
0
-10B
1
L ¹¹
DIMM configuration type
0
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
0
0
07
0D
0B
02
48
00
04
75
80
75
80
02
SDRAM DDR
13
11
2
72 bits
0 (+)
SSTL 2.5V
CL = 2.5*⁵
0.75ns*⁵
0.8ns*⁵
ECC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Refresh rate/type
1 0 0 0 0 0 1 0 82
Primary SDRAM width
0 0 0 0 0 1 0 0 04
Error checking SDRAM width
0 0 0 0 0 1 0 0 04
SDRAM device attributes:
Minimum clock delay back-to-back
P _{column access}
0 0 0 0 0 0 0 1 01
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0E
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04
r _{SDRAM device attributes:}
/CAS latency
o ^{SDRAM device attributes:}
/CS latency
SDRAM device attributes:
/WE latency
0 0 0 0 1 1 0 0 0C
0 0 0 0 0 0 0 1 01
0 0 0 0 0 0 1 0 02
SDRAM module attributes
0 0 1 0 0 1 1 0 26
d _{SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0}
Minimum clock cycle time at
CLX - 0.5
1 0 1 0 0 0 0 0 A0
u ^{Maximum data access time (tAC) from}
clock at CLX - 0.5
0 1 1 1 0 1 0 1 75
-B75B
-10B
1 0 0 0 0 0 0 0 80
Minimum clock cycle time at
c _{CLX - 1}
0 0 0 0 0 0 0 0 00
Maximum data access time (tAC) from
t ^{clock at CLX - 1}
0
0
0
0
0
0
0
0
00
7.8 µs
Self refresh
×4
×4
1 CLK
2, 4, 8
4
2, 2.5
0
1
Registered
± 0.2V
CL = 2*⁵
0.75ns*⁵
0.8ns*⁵
27
Minimum row precharge time (tRP) 0 1 0 1 0 0 0 0 50
20ns
28
Minimum row active to row active
delay (tRRD)
0 0 1 1 1 1 0 0 3C
15ns
29
Minimum /RAS to /CAS delay (tRCD) 0 1 0 1 0 0 0 0 50
20ns
Data Sheet E0089H50 (Ver. 5.0)
5