EBE81AF4ABHA Datasheet, PDF (5/29 Pages) Elpida Memory – 8GB Registered DDR2 SDRAM DIMM

EBE81AF4ABHA
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes utilized by module
manufacturer
1 0 0 0 0 0 0 0 80H
128 bytes
1
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
256 bytes
2
Memory type
0 0 0 0 1 0 0 0 08H
DDR2 SDRAM
3
Number of row address
0 0 0 0 1 1 1 1 0FH
15
4
Number of column address
0 0 0 0 1 0 1 1 0BH
11
5
Number of DIMM ranks
0 1 1 1 0 0 0 1 71H
Stack/2 ranks
6
Module data width
0 1 0 0 1 0 0 0 48H
72
7
Module data width continuation
0 0 0 0 0 0 0 0 00H
0
8
Voltage interface level of this assembly 0 0 0 0 0 1 0 1 05H
SSTL 1.8V
9
DDR SDRAM cycle time, CL = 5
0 0 1 1 0 0 0 0 30H
3.0ns*¹
10
SDRAM access from clock (tAC)
0 1 0 0 0 1 0 1 45H
0.45ns*¹
11
DIMM configuration type
12
Refresh rate/type
0 0 0 0 0 1 1 0 06H
1 0 0 0 0 0 1 0 82H
ECC,
Address/command
Parity
7.8µs
13
Primary SDRAM width
0 0 0 0 0 1 0 0 04H
×4
14
Error checking SDRAM width
0 0 0 0 0 1 0 0 04H
×4
15
Reserved
0 0 0 0 0 0 0 0 00H
0
16
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 0 0 0CH
4,8
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
1
0
0
0
08H
8
18
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 0 0 38H
3, 4, 5
19
DIMM Mechanical Characteristics
0 0 0 0 0 0 1 0 02H
5.1mm max.
20
DIMM type information
0 0 0 0 0 0 0 1 01H
Registered
21
SDRAM module attributes
0 0 0 0 0 0 0 0 00H
Normal
22
SDRAM device attributes: General
0 0 0 0 0 0 1 1 03H
Weak Driver
50Ω ODT Support
23
Minimum clock cycle time at CL = 4
0 0 1 1 1 1 0 1 3DH
3.75ns*¹
24
Maximum data access time (tAC) from
clock at CL = 4
0
1
0
1
0
0
0
0
50H
0.5ns*¹
25
Minimum clock cycle time at CL = 3
0 1 0 1 0 0 0 0 50H
5.0ns*¹
26
Maximum data access time (tAC) from
clock at CL = 3
0
1
1
0
0
0
0
0
60H
0.6ns*¹
27
Minimum row precharge time (tRP)
0 0 1 1 1 1 0 0 3CH
15ns
28
Minimum row active to row active delay
(tRRD)
0
0
0
1
1
1
1
0
1EH
7.5ns
29
Minimum /RAS to /CAS delay (tRCD) 0 0 1 1 1 1 0 0 3CH
15ns
30
Minimum active to precharge time
(tRAS)
0 0 1 0 1 1 0 1 2DH
45ns
31
Module rank density
0 0 0 0 0 1 0 0 04H
4GB
32
Address and command setup time
before clock (tIS)
0 0 1 0 0 0 0 0 20H
0.20ns*¹
33
Address and command hold time after
clock (tIH)
0
0
1
0
0
1
1
1
27H
0.27ns*¹
34
Data input setup time before clock (tDS) 0 0 0 1 0 0 0 0 10H
0.10ns*¹
Data Sheet E1262E30 (Ver. 3.0)
5