EBE81AF4ABHA Datasheet, PDF (26/29 Pages) Elpida Memory – 8GB Registered DDR2 SDRAM DIMM

EBE81AF4ABHA
CKE (input pin)
CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the
CKE is driven low and exited when it resumes to high.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold
time tIH.
DQ, CB (input and output pins)
Data are input to and output from these pins.
DQS (input and output pin)
DQS and /DQS provide the read data strobes (as output) and the write data strobes (as input).
VDD (power supply pins)
1.8V is applied. (VDD is for the internal circuit.)
VDDSPD (power supply pin)
1.8V is applied (For serial EEPROM).
VSS (power supply pin)
Ground is connected.
/RESET(input pin)
LVCMOS reset input. When /RESET is Low, all registers are reset.
Par_IN (Parity input pin)
Parity bit for the address and control bus.
/Err_Out (Error output pin)
Parity error found on the address and control bus.
Detailed Operation Part and Timing Waveforms
Refer to the EDE2104ABSE, EDE2108ABSE datasheet (E1196E). DM pins of component device fixed to VSS level
on the module board. DIMM /CAS latency = component CL + 1 for registered type.
Data Sheet E1262E30 (Ver. 3.0)
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