EDE1108AESE Datasheet, PDF (43/78 Pages) Elpida Memory – 1G bits DDR2 SDRAM

EDE1108AESE, EDE1116AESE
For proper operation of adjust mode, WL = RL − 1 = AL + CL − 1 clocks and tDS/tDH should be met as the Output
Impedance Control Register Set Cycle. For input data pattern for adjustment, DT0 to DT3 is a fixed order and not
affected by MRS addressing mode (i.e. sequential or interleave).
/CK
CK
Command
EMRS
WL
DQS, /DQS
NOP
tDS tDH
EMRS
NOP
tWR
DQ_in
DT0
DT1
DT2
DT3
OCD adjust mode
Output Impedance Control Register Set Cycle
OCD calibration mode exit
Drive Mode
Drive mode, both drive (1) and drive (0), is used for controllers to measure DDR2 SDRAM Driver impedance before
OCD impedance adjustment. In this mode, all outputs are driven out tOIT after “Enter drive mode” command and all
output drivers are turned-off tOIT after “OCD calibration mode exit” command as the ”Output Impedance
Measurement/Verify Cycle”.
/CK
CK
Command
EMRS
High-Z
DQS, /DQS
DQ
tOIT
Enter drivemode
NOP
EMRS
DQs high and /DQS low for drive (1), DQs low and /DQS high for drive (0)
DQs high for drive (1)
DQs low for drive (0)
tOIT
High-Z
OCD Calibration mode exit
Output Impedance Measurement/Verify Cycle
Data Sheet E1290E30 (Ver. 3.0)
43