EDS2532EEBH-75 Datasheet, PDF (42/50 Pages) Elpida Memory – 256M bits SDRAM (8M words x 32 bits)

EDS2532EEBH-75
Write Cycle
CLK
CKE
/CS
/RAS
/CAS
/WE
BS
A10
Address
DQM
tCK
tCH tCL
VIH
tRCD
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI
tRAS
tRC
tRP
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
DQ (input)
DQ (output)
tSI t HI tSI tHI tSI tHI tSI tHI
tDPL
Bank 0
Active
Bank 0
Write
Bank 0
Precharge
CL = 2
BL = 4
Bank 0 access
= VIH or VIL
Mode Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
CKE ^VIH
/CS
/RAS
/CAS
/WE
BS
Address
valid
code
R: b
C: b
C: b’
DQM
DQ (output)
DQ (input)
lRP
Precharge
If needed
Mode
register
Set
lMRD
Bank 3
Active
lRCD
High-Z
Bank 3
Read
b
Output mask
b+3 b’ b’+1 b’+2 b’+3
lRCD = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
Preliminary Data Sheet E0639E50 (Ver. 5.0)
42