EDS2532EEBH-75 Datasheet, PDF (18/50 Pages) Elpida Memory – 256M bits SDRAM (8M words x 32 bits)

EDS2532EEBH-75
Notes: 1. An interval of tDPL is required between the final valid data input and the precharge command.
2. If tRRD is not satisfied, this operation is illegal.
3. Illegal for same bank, except for another bank.
4. Illegal for all banks.
5. NOP for same bank, except for another bank.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. MRS command must be issued after DOUT finished, in case of DOUT remaining.
9. Illegal if lMRD is not satisfied.
Preliminary Data Sheet E0639E50 (Ver. 5.0)
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