EDE5116AJBG-LI Datasheet, PDF (37/76 Pages) Elpida Memory – 512M bits DDR2 SDRAM WTR (Wide Temperature Range)

EDE5116AJBG-LI
Programming the Mode Register and Extended Mode Registers
For application flexibility, burst length, burst type, /CAS latency, DLL reset function, write recovery time (tWR)
are user defined variables and must be programmed with a mode register set command [MRS]. Additionally, DLL
disable function, driver impedance, additive /CAS latency, ODT (On Die Termination), single-ended strobe, and OCD
(Off-Chip Driver Impedance Adjustment) are also user defined variables and must be programmed with an extended
mode register set command [EMRS]. Contents of the Mode Register (MR) or Extended Mode Registers (EMR (#))
can be altered by reexecuting the MRS and EMRS commands. If the user chooses to modify only a subset of the
MRS or EMRS variables, all variables must be redefined when the MRS or EMRS commands are issued.
MRS, EMRS and Reset DLL do not affect array contents, which means reinitialization including those can be
executed any time after power-up without affecting array contents.
DDR2 SDRAM Mode Register Set [MRS]
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls /CAS
latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2
SDRAM useful for various applications. The default value of the mode register is not defined, therefore the mode
register must be written after power-up for proper operation. The mode register is written by asserting low on /CS,
/RAS, /CAS, /WE, BA0 and BA1, while controlling the state of address pins A0 to A12.
The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register.
The mode register set command cycle time (tMRD) is required to complete the write operation to the mode register.
The mode register contents can be changed using the same command and clock cycle requirements during normal
operation as long as all banks are in the precharge state. The mode register is divided into various fields depending
on functionality. Burst length is defined by A0 to A2 with options of 4 and 8 bit burst lengths. The burst length
decodes are compatible with DDR SDRAM. Burst address sequence type is defined by A3, /CAS latency is defined
by A4 to A6. The DDR2 doesn’t support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset.
A7 must be set to low for normal MRS operation. Write recovery time tWR is defined by A9 to A11. Refer to the
table for specific codes.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address field
0*¹ 0 PD
WR
DLL TM /CAS latency BT Burst length Mode register
A8 DLL reset
0
No
1
Yes
A7
Mode
0
Normal
1
Test
BA1 BA0 MRS mode
00
MRS
01
EMRS(1)
10
EMRS(2)
1 1 EMRS(3): Reserved
A12 Active power down exit timing
0 Fast exit (use tXARD timing)
1 Slow exit (use tXARDS timing)
Write recovery for autoprecharge
A11 A10 A9
0
00
0
01
0
10
0
11
1
00
1
01
1
10
1
11
WR
Reserved
2
3
4
5
6
Reserved
Reserved
A3 Burst type
0 Sequential
1
Interleave
Burst length
A2 A1 A0 BL
0 10 4
0 11 8
/CAS latency
A6 A5 A4
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Latency
Reserved
Reserved
Reserved
3
4
5
6
Reserved
Notes: 1. BA1 is reserved for future use and must be programmed to 0 when setting the mode register.
2. WR (min.) (Write Recovery for autoprecharge) is determined by tCK (max.) and WR (max.) is determined by tCK (min.).
WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer
(WR [cycles] = tWR (ns) / tCK (ns)).
The mode register must be programmed to this value. This is also used with tRP to determine tDAL.
Mode Register Set (MRS)
Preliminary Data Sheet E1172E20 (Ver. 2.0)
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