EDE5116AJBG-LI Datasheet, PDF (24/76 Pages) Elpida Memory – 512M bits DDR2 SDRAM WTR (Wide Temperature Range)

Block Diagram
CK
/CK
CKE
A0 to A12, BA0, BA1
/CS
/RAS
/CAS
/WE
EDE5116AJBG-LI
Mode
register
Row
address
buffer
and
refresh
counter
Bank 3
Bank 2
Bank 1
Memory cell array
Bank 0
Column
address
buffer
and
burst
counter
Sense amp.
Column decoder
Data control circuit
Latch circuit
CK, /CK
DLL
Input & Output buffer
DQ
DQS, /DQS
ODT
UDM, LDM
Preliminary Data Sheet E1172E20 (Ver. 2.0)
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