EDE5116AJBG-LI Datasheet, PDF (27/76 Pages) Elpida Memory – 512M bits DDR2 SDRAM WTR (Wide Temperature Range)

EDE5116AJBG-LI
Command Operation
Command Truth Table
The DDR2 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins.
CKE
Function
Previou Current
A12 to
A0 to
Symbol s cycle cycle /CS /RAS /CAS /WE BA0 BA1 A11 A10 A9 Notes
Mode register set
MRS H
H
LLLLL
L
MRS OPCODE
1
Extended mode
register set (1)
Extended mode
register set (2)
EMRS H
EMRS H
H
LLLLH
L
EMRS (1) OPCODE 1
H
LLLLL
H
EMRS (2) OPCODE 1
Auto-refresh
REF H
H
L L L H×
×
×
×
×
1
Self-refresh entry
SELF H
L
L L L H×
×
×
×
×
1
Self-refresh exit
SELFX L
H
H× × × ×
×
×
×
×
1, 6
L
H
L HHH×
×
×
×
×
Single bank precharge
PRE H
H
L L H L BA
×
L
×
1, 2
Precharge all banks
PALL H
H
L L HL ×
×
×
H
×
1
Bank activate
ACT H
H
L L H H BA
RA
1, 2
Write
WRIT H
H
L H L L BA
CA L
CA 1, 2, 3
Write with auto precharge WRITA H
H
L H L L BA
CA H
CA 1, 2, 3
Read
READ H
H
L H L H BA
CA L
CA 1, 2, 3
Read with auto precharge READA H
H
L H L H BA
CA H
CA 1, 2, 3
No operation
NOP H
×
L HHH×
×
×
×
×
1
Device deselect
DESL H
×
H× × × ×
×
×
×
×
1
Power-down mode entry PDEN H
L
H× × × ×
×
×
×
×
1, 4
H
L
L HHH×
×
×
×
×
Power-down mode exit
PDEX L
H
H× × × ×
×
×
×
×
1, 4
L
H
L HHH×
×
×
×
×
Remark: H = VIH. L = VIL. × = VIH or VIL. BA = Bank Address, RA = Row Address, CA = Column Address
Notes: 1. All DDR2 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the
clock.
2. Bank select (BA0, BA1), determine which bank is to be operated upon.
3. Burst reads or writes should not be terminated other than specified as ″Reads interrupted by a Read″ in
burst read command [READ] or ″Writes interrupted by a Write″ in burst write command [WRIT].
4. The power-down mode does not perform any refresh operations. The duration of power-down is therefore
limited by the refresh requirements of the device. One clock delay is required for mode entry and exit.
5. The state of ODT does not affect the states described in this table. The ODT function is not available
during self-refresh.
6. Self-refresh exit is asynchronous.
Preliminary Data Sheet E1172E20 (Ver. 2.0)
27