EDE5104GASA Datasheet, PDF (26/45 Pages) Elpida Memory – 512M bits DDR-II SDRAM

EDE5104GASA, EDE5108GASA
Bank Activate Command [ACT]
The bank activate command is issued by holding /CAS and /WE High with /CS and /RAS Low at the rising edge of
the clock. The bank addresses BA0 and BA1, are used to select the desired bank. The row address A0 through
A12 is used to determine which row to activate in the selected bank. The Bank activate command must be applied
before any read or write operation can be executed. Immediately after the bank active command, the DDR-II
SDRAM can accept a read or write command on the following clock cycle. If a R/W command is issued to a bank
that has not satisfied the tRCD (min.) specification, then additive latency must be programmed into the device to
delay when the R/W command is internally issued to the device. The additive latency value must be chosen to
assure tRCD (min.) is satisfied. Additive latencies of 0, 1 and 2 are supported. Once a bank has been activated it
must be precharged before another bank activate command can be applied to the same bank. The bank active and
precharge times are defined as tRAS and tRP, respectively. The minimum time interval between successive bank
activate commands to the same bank is determined by the /RAS cycle time of the device (tRC), which is equal to
tRAS + tRP. The minimum time interval between successive bank activate commands to the different bank is
E^{determined by (tRRD).}
/CK
O_CK
L ^Command
T0
ACT
T1
T2
Posted
READ
ACT
tRCD(min.)
T3
Posted
READ
Tn
Tn+1 Tn+2 Tn+3
PRE
PRE
ACT
Address ROW: 0 COL: 0 ROW: 1 COL: 1
ROW: 0
tRCD =1
tCCD
Additive latency (AL)
Bank0 Read begins
tRRD
tRAS
tRP
P _tRC
Bank0
Active
Bank1
Active
Bank0
Precharge
Bank1
Bank0
Precharge Active
roduct ^{Bank Activate Command Cycle (tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2)}
Preliminary Data Sheet E0203E41 (Ver. 4.1)
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