EDE5104GASA Datasheet, PDF (1/45 Pages) Elpida Memory – 512M bits DDR-II SDRAM

PRELIMINARY DATA SHEET
512M bits DDR-II SDRAM
EEDDEE55110048GGAASSAA((16248MMwwoorrddss_{××84bbititss)) Description}
The EDE5104GA is a 512M bits DDR-II SDRAM
organized as 33,554,432 words × 4 bits × 4 banks.
EThe EDE5108GA is a 512M bits DDR-II SDRAM
organized as 16,777,216 words × 8 bits × 4 banks.
It is packaged in 60-ball FBGA package.
Features
O_{• 1.8V power supply}
• Double-data-rate architecture: two data transfers per
clock cycle
L ^{• Bi-directional, differential data strobe (DQS and}
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA
1
2
3
7
8
9
A
VDD
NU/ /RDQS
(NC)*
VSS
B
C
DQ6
(NC)*
VSSQ
DM/RDQS
(DM)*
VDDQ DQ1 VDDQ
D
DQ4
(NC)*
VSSQ
DQ3
E
VSSQ /DQS VDDQ
DQS
VSSQ
DQ7
(NC)*
VDDQ DQ0 VDDQ
DQ2
VSSQ
DQ5
(NC)*
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
P ^transitions
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
r ^{• Data mask (DM) for write data}
• Burst lengths: 4 only
• /CAS Latency (CL): 3, 4
o _{• Auto precharge operation for each burst access}
• Auto refresh and self refresh modes
• 7.8µs maximum average periodic refresh interval
d ^{• 1.8V (SSTL_18 compatible) I/O}
• Off-Chip-Driver Impedance Adjustment for better
signal quality.
• Programmable RDQS, /RDQS output for the
u ^{compatibility to × 4 organization}
• /DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
ct ^{• FBGA package is lead free solder (Sn-Ag-Cu)}
VDDL VREF VSS
F
CKE /WE
G
NC BA0 BA1
H
A10 A1
J
VSS A3 A5
K
A7 A9
L
VDD A12 NC
VSSDL CK
/RAS /CK
/CAS /CS
A2 A0
A6 A4
A11 A8
NC NC
(Top view)
Note: ( )* marked pins are for EDE5104GA.
VDD
NC
VDD
VSS
A0 to A12
BA0, BA1
DQ0 to DQ7
DQS, /DQS
RDQS, /RDQS
/CS
/RAS, /CAS, /WE
CKE
CK, /CK
DM
VDD
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
NC*¹
Address input
Bank select address
Data-input/output
Differential data strobe
Differential data strobe for read
Chip select
Command input
Clock enable
Differential Clock input
Output mask
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
Reference supply voltage
Power for DLL circuit
Ground for DLL circuit
No connection
NU*²
Not usable
Notes: 1. Not internally connected with die.
2. Don't connect. Internally connected with die.
Document No. E0203E41 (Ver. 4.1) _{This product became EOL in March, 2004.}
Date Published February 2006 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2006