HB54A2569F1 Datasheet, PDF (1/17 Pages) Elpida Memory – 256MB, 512MB Registered DDR SDRAM DIMM

DATA SHEET
256MB, 512MB Registered DDR SDRAM DIMM
HHBB5544AA52152699FF21((6342MMwwoorrddss××7722bbititss,,21BBaannkks)) _Description
The HB54A2569F1, HB54A5129F2 are Double Data
Rate (DDR) SDRAM Module, mounted 256M bits DDR
ESDRAM (HM5425801BTT) sealed in TSOP package, 1
piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD).
O^{The HB54A2569F1 is organized as 32M × 72 × 1 bank}
mounted 9 pieces of 256M bits DDR SDRAM. The
HB54A5129F2 is organized as 32M × 72 × 2 banks
mounted 18 pieces of 256M bits DDR SDRAM. Read
and write operations are performed at the cross points
of the CK and the /CK. This high-speed data transfer
L _{is realized by the 2 bits prefetch-pipelined architecture.}
Data strobe (DQS) both for read and write are available
for high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. An outline of
the products is 184-pin socket type package (dual lead
P out). Therefore, it makes high density mounting
possible without surface mount technology. It provides
common data inputs and outputs. Decoupling
capacitors are mounted beside each TSOP on the
roduct ^{module board.}
Features
• 184-pin socket type package (dual lead out)
 Outline: 133.35mm (Length) × 43.18mm (Height) ×
4.00mm (Thickness)
 Lead pitch: 1.27mm
• 2.5V power supply (VCC/VCCQ)
• SSTL-2 interface for all inputs and outputs
• Clock frequency: 143MHz/133MHz/125MHz (max.)
• Data inputs, outputs and DM are synchronized with
DQS
• 4 banks can operate simultaneously and
independently (Component)
• Burst read/write operation
• Programmable burst length: 2, 4, 8
 Burst read stop capability
• Programmable burst sequence
 Sequential
 Interleave
• Start addressing capability
 Even and Odd
• Programmable /CAS latency (CL): 3, 3.5
• 8192 refresh cycles: 7.8µs (8192/64ms)
• 2 variations of refresh
 Auto refresh
 Self refresh
Document No. E0091H40 (Ver. 4.0) _{This product became EOL in May, 2004.}
Date Published September 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
Hitachi, Ltd. 2001
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.