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GD25LQ40 Datasheet, PDF (8/59 Pages) ELM Electronics – 1.8V Uniform Sector Dual and Quad Serial Flash | |||
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GD25LQ40xIGx 1.8V Uniform Sector Dual and Quad Serial Flash
http://www.elm-tech.com
Figure 1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
5. DATA PROTECTION
The GD25LQ40 provides the following data protection methods:
⦠Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
- Power-Up / Write Disable (WRDI) / Write Status Register (WRSR)
- Page Program (PP) / Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
⦠Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the
memory array that can be read but not change.
⦠Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
⦠Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down Mode command.
Table 1. GD25LQ40 Protected area size (CMP=0)
Status Register Content
Memory Content
BP4 BP3 BP2 BP1 BP0
ÃÃ000
00001
00010
00011
01001
01010
01011
0Ã1ÃÃ
10001
10010
10011
1010Ã
10110
11001
11010
11011
1110Ã
11110
1Ã111
Blocks
NONE
7
6 and 7
4 to 7
0
0 and 1
0 to 3
0 to 7
7
7
7
7
7
0
0
0
0
0
0 to 7
Addresses
NONE
070000H-07FFFFH
060000H-07FFFFH
040000H-07FFFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-03FFFFH
000000H-07FFFFH
07F000H-07FFFFH
07E000H-07FFFFH
07C000H-07FFFFH
078000H-07FFFFH
078000H-07FFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
000000H-007FFFH
000000H-07FFFFH
Density
NONE
64KB
128KB
256KB
64KB
128KB
256KB
512KB
4KB
8KB
16KB
32KB
32KB
4KB
8KB
16KB
32KB
32KB
512KB
Portion
NONE
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/8
Lower 1/4
Lower 1/2
ALL
Upper 1/128
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/16
Lower 1/128
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/16
ALL
59 - 8
Rev.1.0
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