MA31755 Datasheet, PDF (3/13 Pages) Dynex Semiconductor – 16-Bit Feedthrough Error Detection & Correction Unit EDAC

MA31755
2.2 BUS CONTROL
There are four signals which control the drive status of the EDAC external busses: RDWN, CS2N, CS1N and CS0. The
relationship to each other and to the EDAC busses is shown in Figure 2 below. The timing of these signals is shown in Figures 6
and 7.
RDWN
X
X
X
High
Low
CS2N
High
X
X
Low
Low
CS1N
X
High
X
Low
Low
CS0
X
X
Low
High
High
Bus state
Processor Memory
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Output
Input
Input
Output
Figure 2: Bus Control
2.3 INTERNAL OPERATION
2.3.1 Check Bit Generation
On write cycles the processor data word, PD[0:15], and the processor parity bit ,PD[16], are passed directly to the memory
data bus, MD[0:15], and the memory parity bit, MD[16].
The check bits, CB[0:5], are derived by 6 parity generators operating on sets of 8 bits of the processor data word, PD[0:15], as
shown in Figure 3 below:
CB Parity
0
Even
1
Even
2
Odd
3
Odd
4
Even
5
Even
PD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XX
XXXXX
X
X
XXXX
X
X
X
X
X
X
X
XXXX
XX
X
XXXXX
X
XXXXX
X
X
XXXXX
XX
X
Figure 3: Check Bit Generation
2.3.2 Syndrome Generation
The syndrome generation logic checks the sense of the check bits with respect to the memory data word. Six 9-input parity
checkers generate the syndrome bits, SY[0:5], according to figure 4 below:
S Y Parity
0
Even
1
Even
2
Odd
3
Odd
4
Even
5
Even
MD
CB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5
XX
XXXXX
XX
X
XXXX
X
X
X
X
X
X
X
X
XXXX
X
XX
X
XXXXX
X
X
XXXXX
X
X
X
XXXXX
XX
X
X
Figure 4: Syndrome Generation
If there are no errors in the memory data word, MD[0:15],
or the check bits, CB[0:5], then all of the syndrome bits,
SY[0:5], will be set low.
A single bit error in the memory data word, MD[0:15], will
cause 3 syndrome bits to be set high. However, a single bit
error in the check bits, CB[0:5], will cause only 1 syndrome bit
to be set high. A two bit error in the memory data word and/or
the check bits will cause either 2, 4, 5 or 6 syndrome bits to be
set.
Three or more errors in the memory data word and/or the
check bits will cause an undefined number of syndrome bits to
be set. This will cause the operation of the device in respect of
the states of CERRN, NCERRN and data on the PD bus to be
unpredictable.
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