DA14581 Datasheet, PDF (91/152 Pages) Dialog Semiconductor – Low Power Bluetooth Smart SoC with optimized boot time

DA14581
Low Power Bluetooth Smart SoC with optimized boot time
FINAL
Table 116: UART2_SRTS_REG (0x5000118C)
Bit
Mode Symbol
Description
0
R/W UART_SHADOW_R Shadow Request to Send.
EQUEST_TO_SEND This is a shadow register for the RTS bit (MCR[1]), this can
be used to remove the burden of having to perform a read-
modify-write on the MCR. This is used to directly control the
Request to Send (rts_n) output. The Request To Send
(rts_n) output is used to inform the modem or data set that
the UART Ctrl is ready to exchange data.
When Auto Flow Control is disabled (MCR[5] = 0), the rts_n
signal is set low by programming MCR[1] (RTS) to a high.
When Auto Flow Control is enabled (MCR[5] = 1) and FIFOs
are enabled (FCR[0] = 1), the rts_n output is controlled in the
same way, but is also gated with the receiver FIFO threshold
trigger (rts_n is inactive high when above the threshold).
Note that in Loopback mode (MCR[4] = 1), the rts_n output is
held inactive-high while the value of this location is internally
looped back to an input.
Reset
0x0
Table 117: UART2_SBCR_REG (0x50001190)
Bit
Mode Symbol
Description
15:1 -
-
Reserved
0
R/W UART_SHADOW_B Shadow Break Control Bit.
REAK_CONTROL
This is a shadow register for the Break bit (LCR[6]), this can
be used to remove the burden of having to performing a read
modify write on the LCR. This is used to cause a break con-
dition to be transmitted to the receiving device.
If set to one the serial output is forced to the spacing (logic 0)
state. When not in Loopback Mode, as determined by
MCR[4], the sout line is forced low until the Break bit is
cleared.
If SIR_MODE active (MCR[6] = 1) the sir_out_n line is con-
tinuously pulsed. When in Loopback Mode, the break condi-
tion is internally looped back to the receiver.
Reset
0x0
0x0
Table 118: UART2_SDMAM_REG (0x50001194)
Bit
Mode Symbol
Description
15:1 -
-
Reserved
0
R/W UART_SHADOW_D Shadow DMA Mode.
MA_MODE
This is a shadow register for the DMA mode bit (FCR[3]).
This can be used to remove the burden of having to store the
previously written value to the FCR in memory and having to
mask this value so that only the DMA Mode bit gets updated.
This determines the DMA signalling mode used for the
dma_tx_req_n and dma_rx_req_n output signals.
0 = mode 0
1 = mode 1
Reset
0x0
0x0
Table 119: UART2_SFE_REG (0x50001198)
Bit
Mode Symbol
15:1 -
-
Description
Reserved
Reset
0x0
Datasheet
CFR0011-120-00-FM Rev 5
Revision 3.0
91 of 152
18-Dec-2015
© 2015 Dialog Semiconductor