DA14581 Datasheet, PDF (100/152 Pages) Dialog Semiconductor – Low Power Bluetooth Smart SoC with optimized boot time

DA14581
Low Power Bluetooth Smart SoC with optimized boot time
FINAL
Table 139: I2C_INTR_STAT_REG (0x5000132C)
Bit
Mode Symbol
2
R
R_RX_FULL
1
R
R_RX_OVER
0
R
R_RX_UNDER
Description
Set when the receive buffer reaches or goes above the
RX_TL threshold in the I2C_RX_TL register. It is automati-
cally cleared by hardware when buffer level goes below the
threshold. If the module is disabled (I2C_ENABLE[0]=0), the
RX FIFO is flushed and held in reset; therefore the RX FIFO
is not full. So this bit is cleared once the I2C_ENABLE bit 0 is
programmed with a 0, regardless of the activity that contin-
ues.
Set if the receive buffer is completely filled to 32 and an addi-
tional byte is received from an external I2C device. The con-
troller acknowledges this, but any data bytes received after
the FIFO is full are lost. If the module is disabled
(I2C_ENABLE[0]=0), this bit keeps its level until the master
or slave state machines go into idle, and when ic_en goes to
0, this interrupt is cleared.
Set if the processor attempts to read the receive buffer when
it is empty by reading from the IC_DATA_CMD register. If the
module is disabled (I2C_ENABLE[0]=0), this bit keeps its
level until the master or slave state machines go into idle,
and when ic_en goes to 0, this interrupt is cleared.
Reset
0x0
0x0
0x0
Table 140: I2C_INTR_MASK_REG (0x50001330)
Bit
15:12
11
Mode
-
R/W
Symbol
-
M_GEN_CALL
10
R/W M_START_DET
9
R/W M_STOP_DET
8
R/W M_ACTIVITY
7
R/W M_RX_DONE
6
R/W M_TX_ABRT
5
R/W M_RD_REQ
4
R/W M_TX_EMPTY
3
R/W M_TX_OVER
2
R/W M_RX_FULL
1
R/W M_RX_OVER
0
R/W M_RX_UNDER
Description
Reserved
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
Reset
0x0
0x1
0x0
0x0
0x0
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
Datasheet
CFR0011-120-00-FM Rev 5
Revision 3.0
100 of 152
18-Dec-2015
© 2015 Dialog Semiconductor