DA14581 Datasheet, PDF (5/152 Pages) Dialog Semiconductor – Low Power Bluetooth Smart SoC with optimized boot time

DA14581
Low Power Bluetooth Smart SoC with optimized boot time
FINAL
Table 1: Pin description
PIN NAME
TYPE
General Purpose I/Os
P0_0
DIO
P0_1
DIO
P0_2
DIO
P0_3
DIO
P0_4
DIO
P0_5
DIO
P0_6
DIO
P0_7
DIO
P1_0
DIO
P1_1
DIO
P1_2
DIO
P1_3
DIO
P1_4/SWCLK
DIO
P1_5/SW_DIO DIO
P2_0
DIO
P2_1
DIO
P2_2
DIO
P2_3
DIO
P2_4
DIO
P2_5
DIO
P2_6
DIO
P2_7
DIO
P2_8
DIO
P2_9
DIO
P3_0 to P3_7
DIO
Debug interface
SWDIO/P1_5
DIO
Drive
(mA)
4.8
4.8
4.8
4.8
4.8
SW_CLK/
P1_4
DIO
4.8
Clocks
XTAL16Mp
AI
XTAL16Mm
AO
XTAL32kp
AI
XTAL32km
AO
Quadrature decoder
QD_CHA_X
DI
QD_CHB_X
DI
QD_CHA_Y
DI
QD_CHB_Y
DI
QD_CHA_Z
DI
QD_CHB_Z
DI
SPI bus interface
SPI_CLK
DO
SPI_DI
DI
Datasheet
CFR0011-120-00-FM Rev 5
Reset
state
(Note )
DESCRIPTION
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PU
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
This signal is the JTAG clock by default
This signal is the JTAG data I/O by default
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
NOTE: This port is only available on the QFN40 package.
Not supported.
I-PU
I-PD
INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and
control communication. Can also be used as a GPIO
INPUT JTAG clock signal. Can also be used as a GPIO
INPUT. Crystal input for the 16 MHz XTAL
OUTPUT. Crystal output for the 16 MHz XTAL
INPUT. Crystal input for the 32.768 kHz XTAL
OUTPUT. Crystal output for the 32.768 kHz XTAL
INPUT. Channel A for the X axis. Mapped on Px ports
INPUT. Channel B for the X axis. Mapped on Px ports
INPUT. Channel A for the Y axis. Mapped on Px ports
INPUT. Channel B for the Y axis. Mapped on Px ports
INPUT. Channel A for the Z axis. Mapped on Px ports
INPUT. Channel B for the Z axis. Mapped on Px ports
INPUT/OUTPUT. SPI Clock. Mapped on Px ports
INPUT. SPI Data input. Mapped on Px ports
Revision 3.0
5 of 152
18-Dec-2015
© 2015 Dialog Semiconductor