DA14583_16 Datasheet, PDF (35/150 Pages) Dialog Semiconductor – Bluetooth Low Energy 4.2 SoC with Flash Memory

DA14583
Bluetooth Low Energy 4.2 SoC with Flash Memory
FINAL
Table 42: QDEC_YCNT_REG (0x50000204)
Bit
Mode Symbol
15:0 r
Y_COUNTER
Description
Contains a signed value of the events. Zero when channel is
disabled
Reset
0x0
Table 43: QDEC_CLOCKDIV_REG (0x50000206)
Bit
Mode Symbol
9:0
r/w
CLOCK_DIVIDER
Description
Contains the number of the input clock cycles minus one,
that are required to generate one logic clock cycle.
Reset
0x0
Table 44: QDEC_CTRL2_REG (0x50000208)
Bit
15:12
11:8
Mode
-
r/w
Symbol
-
CHZ_PORT_SEL
7:4
r/w
CHY_PORT_SEL
3:0
r/w
CHX_PORT_SEL
Description
Reserved
Defines which GPIOs are mapped on Channel Z
0: none
1: P0[0] -> CHZ_A, P0[1] -> CHZ_B
2: P0[2] -> CHZ_A, P0[3] -> CHZ_B
3: P0[4] -> CHZ_A, P0[5] -> CHZ_B
4: P0[6] -> CHZ_A, P0[7] -> CHZ_B
5: P1[0] -> CHZ_A, P1[1] -> CHZ_B
6: P1[2] -> CHZ_A, P1[3] -> CHZ_B
7: P2[3] -> CHZ_A, P2[4] -> CHZ_B
8: P2[5] -> CHZ_A, P2[6] -> CHZ_B
9: P2[7] -> CHZ_A, P2[8] -> CHZ_B
10: P2[9] -> CHZ_A, P2[0] -> CHZ_B
11..15: None
Defines which GPIOs are mapped on Channel Y
0: none
1: P0[0] -> CHY_A, P0[1] -> CHY_B
2: P0[2] -> CHY_A, P0[3] -> CHY_B
3: P0[4] -> CHY_A, P0[5] -> CHY_B
4: P0[6] -> CHY_A, P0[7] -> CHY_B
5: P1[0] -> CHY_A, P1[1] -> CHY_B
6: P1[2] -> CHY_A, P1[3] -> CHY_B
7: P2[3] -> CHY_A, P2[4] -> CHY_B
8: P2[5] -> CHY_A, P2[6] -> CHY_B
9: P2[7] -> CHY_A, P2[8] -> CHY_B
10: P2[9] -> CHY_A, P2[0] -> CHY_B
11..15: None
Defines which GPIOs are mapped on Channel X
0: none
1: P0[0] -> CHX_A, P0[1] -> CHX_B
2: P0[2] -> CHX_A, P0[3] -> CHX_B
3: P0[4] -> CHX_A, P0[5] -> CHX_B
4: P0[6] -> CHX_A, P0[7] -> CHX_B
5: P1[0] -> CHX_A, P1[1] -> CHX_B
6: P1[2] -> CHX_A, P1[3] -> CHX_B
7: P2[3] -> CHX_A, P2[4] -> CHX_B
8: P2[5] -> CHX_A, P2[6] -> CHX_B
9: P2[7] -> CHX_A, P2[8] -> CHX_B
10: P2[9] -> CHX_A, P2[0] -> CHX_B
11..15: None
Reset
0
0
0
0
Datasheet
CFR0011-120-01
Revision 3.0
35 of 150
04-Nov-2016
© 2014 Dialog Semiconductor