DA14582 Datasheet, PDF (141/177 Pages) Dialog Semiconductor – Low Power Bluetooth Smart SoC with Audio Codec

Table 225: KBRD_IRQ_IN_SEL2_REG (0x50001416)
Bit
Mode Symbol
7
R/W KBRD_P37_EN
6
R/W KBRD_P36_EN
5
R/W KBRD_P35_EN
4
R/W KBRD_P34_EN
3
R/W KBRD_P33_EN
2
R/W KBRD_P32_EN
1
R/W KBRD_P31_EN
0
R/W KBRD_P30_EN
Description
enable P3[7] for the keyboard interrupt
enable P3[6] for the keyboard interrupt
enable P3[5] for the keyboard interrupt
enable P3[4] for the keyboard interrupt
enable P3[3] for the keyboard interrupt
enable P3[2] for the keyboard interrupt
enable P3[1] for the keyboard interrupt
enable P3[0] for the keyboard interrupt
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Table 226: GP_ADC_CTRL_REG (0x50001500)
Bit
Mode Symbol
Description
Reset
15
R/W GP_ADC_LDO_ZERO Forces LDO-output to 0V.
0x0
14
R/W GP_ADC_LDO_EN Turns on LDO.
0x0
13
R/W GP_ADC_CHOP
Takes two samples with opposite GP_ADC_SIGN to cancel 0x0
the internal offset voltage of the ADC; Highly recommended
for DC-measurements.
12
R/W GP_ADC_MUTE
Takes sample at mid-scale (to dertermine the internal offset 0x0
and/or noise of the ADC with regards to VDD_REF which is
also sampled by the ADC).
11
R/W GP_ADC_SE
0 = Differential mode
0x0
1 = Single ended mode
10
R/W GP_ADC_SIGN
0 = Default
0x0
1 = Conversion with opposite sign at input and output to can-
cel out the internal offset of the ADC and low-frequency
9:6
R/W GP_ADC_SEL
ADC input selection which must be set before the
0x0
GP_ADC_START bit is enabled.
If GP_ADC_SE = 1 (single ended mode):
0000 = P0[0]
0001 = P0[1]
0010 = P0[2]
0011 = P0[3]
0100 = AVS
0101 = VDD_REF
0110 = VDD_RTT
0111 = VBAT3V
1000 = VDCDC
1001 = VBAT1V
All other combinations are reserved.
If GP_ADC_SE = 0 (differential mode):
0000 = P0[0] vs P0[1]
All other combinations are P0[2] vs P0[3].
5
R/W GP_ADC_MINT
0 = Disable (mask) GP_ADC_INT.
0x0
1 = Enable GP_ADC_INT to ICU.
4
R
GP_ADC_INT
1 = AD conversion ready and has generated an interrupt.
0x0
Must be cleared by writing any value to
GP_ADC_CLEAR_INT_REG.
3
R/W GP_ADC_CLK_SEL 0 = Internal high-speed ADC clock used.
0x0
1 = Digital clock used.
2
-
GP_ADC_TEST
Reserved, keep 0.
0x0
© 2015 Dialog Semiconductor
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Preliminary - March 11, 2015 v2.0