DA14582 Datasheet, PDF (130/177 Pages) Dialog Semiconductor – Low Power Bluetooth Smart SoC with Audio Codec

Table 191: I2C_RAW_INTR_STAT_REG (0x50001334)
Bit
Mode Symbol
2
R
RX_FULL
1
R
RX_OVER
0
R
RX_UNDER
Description
Set when the receive buffer reaches or goes above the
RX_TL threshold in the I2C_RX_TL register. It is automati-
cally cleared by hardware when buffer level goes below the
threshold. If the module is disabled (I2C_ENABLE[0]=0), the
RX FIFO is flushed and held in reset; therefore the RX FIFO
is not full. So this bit is cleared once the I2C_ENABLE bit 0 is
programmed with a 0, regardless of the activity that contin-
ues.
Set if the receive buffer is completely filled to 32 and an addi-
tional byte is received from an external I2C device. The con-
troller acknowledges this, but any data bytes received after
the FIFO is full are lost. If the module is disabled
(I2C_ENABLE[0]=0), this bit keeps its level until the master or
slave state machines go into idle, and when ic_en goes to 0,
this interrupt is cleared.
Set if the processor attempts to read the receive buffer when
it is empty by reading from the IC_DATA_CMD register. If the
module is disabled (I2C_ENABLE[0]=0), this bit keeps its
level until the master or slave state machines go into idle, and
when ic_en goes to 0, this interrupt is cleared.
Reset
0x0
0x0
0x0
Table 192: I2C_RX_TL_REG (0x50001338)
Bit
Mode Symbol
15:5 -
-
4:0
R/W RX_TL
Description
Reserved
Receive FIFO Threshold Level Controls the level of entries
(or above) that triggers the RX_FULL interrupt (bit 2 in
I2C_RAW_INTR_STAT register). The valid range is 0-31, with
the additional restriction that hardware does not allow this
value to be set to a value larger than the depth of the buffer. If
an attempt is made to do that, the actual value set will be the
maximum depth of the buffer. A value of 0 sets the threshold
for 1 entry, and a value of 31 sets the threshold for 32 entries.
Reset
0x0
0x0
Table 193: I2C_TX_TL_REG (0x5000133C)
Bit
Mode Symbol
15:5 -
-
4:0
R/W RX_TL
Description
Reserved
Transmit FIFO Threshold Level Controls the level of entries
(or below) that trigger the TX_EMPTY interrupt (bit 4 in
I2C_RAW_INTR_STAT register). The valid range is 0-31, with
the additional restriction that it may not be set to value larger
than the depth of the buffer. If an attempt is made to do that,
the actual value set will be the maximum depth of the buffer. A
value of 0 sets the threshold for 0 entries, and a value of 31
sets the threshold for 32 entries..
Reset
0x0
0x0
Table 194: I2C_CLR_INTR_REG (0x50001340)
Bit
Mode Symbol
15:1 -
-
Description
Reserved
Reset
0x0
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