DR80390_1 Datasheet, PDF (6/8 Pages) Digital Core Design – High Performance 8-bit Microcontroller ver 3.10

PERFORMANCE
The following tables give a survey about the
Core area and performance in ASICs Devices
(CPU features and peripherals have been in-
cluded):
Device
Optimization
0.25u typical
area
F_max
100 MHz
0.25u typical
speed
250 MHz
Core performance in ASIC devices
For a user the most important is application
speed improvement. The most commonly used
arithmetic functions and their improvements
are shown in table below. An improvement was
computed as {80C51 clock periods} divided by
{DR80390 clock periods} required to execute
an identical function. More details are available
in core documentation.
Function
8-bit addition (immediate data)
8-bit addition (direct addressing)
8-bit addition (indirect addressing)
8-bit addition (register addressing)
8-bit subtraction (immediate data)
8-bit subtraction (direct addressing)
8-bit subtraction (indirect addressing)
8-bit subtraction (register addressing)
8-bit multiplication
8-bit division
16-bit addition
16-bit subtraction
16-bit multiplication
32-bit addition
32-bit subtraction
32-bit multiplication
Average speed improvement:
Improvement
7,20
6,00
6,00
7,20
7,20
6,00
6,00
7,20
10,67
9,60
7,20
7,64
9,75
7,20
7,43
9,04
7,58
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. The following ta-
ble gives a survey about the DR80390 per-
formance in terms of Dhrystone/sec and VAX
MIPS rating.
Device
Target
Clock
frequency
Dhry/sec
(VAX MIPS)
80C51
-
12 MHz
268 (0.153)
80C310
-
33 MHz 1550 (0.882)
DR80390 0.25u
250 MHz 40125 (22.837)
Core performance in terms of Dhrystones
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
40125
268 ¹⁵⁵⁰
80C51 (12MHz) 80C310 (33MHz) DR80390 (250MHz)
Area utilized by the each unit of DR80390 core
in vendor specific technologies is summarized
in table below.
CPU*
Component
Area
[Gates]
[FFs]
5500
250
Interrupt Controller
450
40
Power Management Unit
50
5
I/O ports
400
35
Timers
550
50
UART0
650
60
Total area
7600
430
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization
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