DR80390_1 Datasheet, PDF (5/8 Pages) Digital Core Design – High Performance 8-bit Microcontroller ver 3.10

program into RAM, EPROM or FLASH
EEPROM storage via UART, SPI, I2C or
DoCD™ module. Program fetch cycle length
can be programmed by user. This feature is
called Program Memory Wait States, and al-
lows core to work with different speed program
memories.
External Memory Interface – Contains mem-
ory access related registers such as Data
Pointer High (DPH0), Data Pointer Low
(DPL0), Data Page Pointer (DPP0), MOVX
@Ri address register (MXAX) and STRETCH
registers. It performs the memory addressing
and data transfers. Allows applications soft-
ware to access up to 16 MB of external data
memory. The DPP0 register is used for seg-
ments swapping. STRETCH register allows
flexible timing management while accessing
different speed system devices by program-
ming XRAMWR and XRAMRD pulse width
between 1 – 8 clock periods.
Internal Data Memory Interface – Internal
Data Memory interface controls access into the
internal 256 bytes memory. It contains 8-bit
Stack Pointer (SP) register and related logic.
User SFRs Interface – Special Function Reg-
isters interface controls access to the special
registers. It contains standard and used de-
fined registers and related logic. User defined
external devices can be quickly accessed
(read, written, modified) using all direct ad-
dressing mode instructions.
Interrupt Controller – Interrupt control module
is responsible for the interrupt manage system
for the external and internal interrupt sources.
It contains interrupt related registers such as
Interrupt Enable (IE), Interrupt Priority (IP) and
(TCON) registers.
I/O Ports – Block contains 8051’s general pur-
pose I/O ports. Each of port’s pin can be
read/write as a single bit or as an 8-bit bus
called P0, P1, P2, P3.
Power Management Unit – Block contains
advanced power saving mechanisms with
switchback feature, allowing external clock
control logic to stop clocking (Stop mode) or
run core in lower clock frequency (Power Man-
agement Mode) to significantly reduce power
consumption. Switchback feature allows
UARTs, and interrupts to be processed in full
speed mode if enabled. It is very desired when
microcontroller is planned to use in portable
and power critical applications.
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DoCD™ Debug Unit – it’s a real-time hard-
ware debugger provides debugging capability
of a whole SoC system. In contrast to other on-
chip debuggers DoCD™ provides non-intrusive
debugging of running application. It can halt,
run, step into or skip an instruction, read/write
any contents of microcontroller including all
registers, internal, external, program memo-
ries, all SFRs including user defined peripher-
als. Hardware breakpoints can be set and con-
trolled on program memory, internal and exter-
nal data memories, as well as on SFRs. Hard-
ware breakpoint is executed if any write/read
occurred at particular address with certain data
pattern or without pattern. The DoCD™ system
includes three-wire interface and complete set
of tools to communicate and work with core in
real time debugging. It is built as scalable unit
and some features can be turned off to save
silicon and reduce power consumption. A spe-
cial care on power consumption has been
taken, and when debugger is not used it is
automatically switched in power save mode.
Finally whole debugger is turned off when de-
bug option is no longer used.
Timers – System timers module. Contains two
16 bits configurable timers: Timer 0 (TH0,
TL0), Timer 1 (TH1, TL1) and Timers Mode
(TMOD) registers. In the timer mode, timer
registers are incremented every 12 CLK peri-
ods when appropriate timer is enabled. In the
counter mode the timer registers are incre-
mented every falling transition on their corre-
sponding input pins (T0, T1), if gates are
opened (GATE0, GATE1). T0, T1 input pins
are sampled every CLK period. It can be used
as clock source for UARTs.
UART0 – Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it
can transmit and receive concurrently. Includes
Serial Configuration register (SCON), serial
receiver and transmitter buffer (SBUF) regis-
ters. Its receiver is double-buffered, meaning it
can commence reception of a second byte
before a previously received byte has been
read from the receive register. Writing to
SBUF0 loads the transmit register, and reading
SBUF0 reads a physically separate receive
register. Works in 3 asynchronous and 1 syn-
chronous modes. UART0 can be synchronized
by Timer 1.
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