D16750 Datasheet, PDF (5/7 Pages) Digital Core Design – Configurable UART with FIFO

Interrupt Controller - D16750 consists fully
prioritized interrupt system controller. It
controls interrupt requests to the CPU and
interrupt priority. Interrupt controller contains
Interrupt Enable (IER) and Interrupt
Identification (IIR) registers.
addr(2:0)
datai(7:0)
datao(7:0)
rd
wr
cs
ddis
txrdy
rxrdy
Data Bus
Buffer
Receiver
Control
&
Shift Register
rclk
rclken
si
RCVR Buffer
&
RCVR FIFO
rts
cts
dtr
dsr
dcd
ri
out1
out2
baudclk
baudclken
baudout
clk
rst
Modem
control
logic
Baud
Generator
Transmitter
Control
&
so
Shift Register
THR Buffer
&
THR FIFO
Interrupt
Controller
intr
Receiver Control - Receiving starts when the
falling edge on Serial Input (SI) during IDLE
State is detected. After starting the SI input is
sampled every 16 internal baud cycles as it is
shown in figure below. When the logic 1 state
is detected during START bit it means that the
False Start bit was detected and receiver back
to the IDLE state.
Receiver FIFO - The Rx FIFO can be 64
(128, 256, 512) levels deep, it receives data
until the number of bytes in the FIFO equals
the selected interrupt trigger level. At that time
if Rx interrupts are enabled, the UART will
issue an interrupt to the CPU. The Rx FIFO
will continue to store bytes until it is full, and
will not accept any next byte. Any more data
entering the Rx shift register will set the
Overrun Error flag.
Transmitter Control module controls
transmission of written to THR (Transmitter
Holding register) character via serial output
SO. The new transmission starts on the next
overflow signal of internal baud generator,
after writing to THR register or Transmitter
FIFO. Transmission control contains THR
register and transmitter shift register.
Transmitter FIFO - the Tx portion of the
UART transmits data through SO as soon as
the CPU loads a byte into the Tx FIFO. The
UART will prevent loads to the Tx FIFO if it
currently holds 64 (128, 256, 512) characters
(depending on FCR(5) bit value and selected
FIFO size). Loading to the Tx FIFO will again
be enabled as soon as the next character is
transferred to the Tx shift register. These
capabilities account for the largely
autonomous operation of the Tx. The UART
starts the above operations typically with a Tx
interrupt.
PERFORMANCE
The following table gives a survey about
the Core area and performance in the
ALTERA® devices after Place & Route:
Device
Speed
grade
Logic Cells
F_max
CYCLONE
-6
484¹
149 MHz
CYCLONE2 -6
499¹
160 MHz
STRATIX
-5
484¹
158 MHz
STRATIX2
-3
418¹
255 MHz
STRATIXGX -5
484¹
163 MHz
MERCURY
-5
540¹
136 MHz
EXCALIBUR -1
511¹
112 MHz
APEX II
-7
512¹
145 MHz
APEX20KC -7
511¹
135 MHz
APEX20KE -1
511¹
96 MHz
APEX20K
-1
511¹
87 MHz
ACEX1K
-1
543¹
93 MHz
FLEX10KE
-1
543¹
94 MHz
1_{- FIFOs implemented in EAB’s – 1216 Bits}
Core performance in ALTERA® devices
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.