D16750 Datasheet, PDF (3/7 Pages) Digital Core Design – Configurable UART with FIFO

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environment
◊ Active-HDL automatic simulation macros
◊ ModelSim automatic simulation macros
◊ Tests with reference responses
♦ Technical documentation
◊ Installation notes
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◊ Datasheet
♦ Synthesis scripts
♦ Example application
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◊ 3 months maintenance
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and major versions changes
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CONFIGURATION
The following parameters of the D16750 core
can be easy adjusted to requirements of
dedicated application and technology.
Configuration of the core can be prepared by
effortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
• Baud generator
- enable
- disable
• External RCLK source
- enable
- disable
• External BAUDCLK source
- enable
- disable
• Modem Control logic
- enable
- disable
• SCR Register
- enable
- disable
• FIFO Control logic
- enable
- disable
• FIFO size
- standard 16/64
- large up to 512
DESIGN FEATURES
The functionality of the D16750 core was
based on the Texas Instruments TL16C750A.
The following characteristics differentiate the
D16750 from Texas Instruments devices:
● The bi-directional data bus has been split
into two separate buses: datai(7:0),
datao(7:0)
● Signals rd2 and wr2, xin, and xout have
been removed from interface
● Signal ADS and address latch have been
removed
● The DLL, DLM and THR registers are
reset to all zeros
● TEMT and THRE bits of Line Status
Register, are reset during the second
clock rising edge following a THR write
● RCLK clock is replaced by global clock
CLK, internally divided by BAUD factor.
● Asynchronous microcontroller interface is
replaced by equivalent Universal interface
● All latches implemented in original 16750
devices are replaced by equivalent flip-flop
registers, with the same functionality
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