D16750 Datasheet, PDF (4/7 Pages) Digital Core Design – Configurable UART with FIFO

SYMBOL
rst
clk
rclk
baudclk
baudout
intr
datai(7:0)
address(2:0)
datao(7:0)
wr
ddis
rd
D16750
txrdy
cs
rxrdy
si
so
cts
rts
dsr
dtr
dcd
out1
ri
out2
baudclken
rclken
PINS DESCRIPTION
PIN
TYPE
DESCRIPTION
rst
input Global reset
clk
input Global clock
datai[7:0]
input Parallel data input
addr[2:0]
input Address bus
cs
input Chip select input
wr
input Write input
rd
input Read input
rclk
input Receiver clock
baudclk
input Baud generator clock
si
input Serial data input
cts
input Clear to send input
dsr
input Data set ready input
dcd
input Data carrier detect input
ri
input Ring indicator input
baudclken
input Baud generator clock enable
rclken
input Receiver clock enable
baudout
output Baud generator output
datao[7:0]
output Parallel data output
so
output Serial data output
ddis
output Driver disable output
txrdy
output Transmitter ready output
rxrdy
output Receiver ready output
rts
output Request to send output
dtr
output Data terminal ready output
out1
output Output 1
out2
output Output 2
intr
output Interrupt request output
Note: When enabled RCLK and BAUDCLK pins
frequency should be at least two times lower
than CLK, 2*f_RCLK< f_CLK
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APPLICATION
addr
CPU ale
addr
latch
datao(7:0)
datai(7:0)
we
rd
cs
int
addr(2:0)
D16750
clk
rst
baudclk
rclk
datai(7:0)
so
datao(7:0)
si
wr
rts
rd
dtr
cs
dsr
intr
dcd
cts
rxrdy
ri
txrdy
out1 baudclken
out2
rclken
EIA
Drivers
Typical D16750 and processor connection is
shown in figure above.
BLOCK DIAGRAM
Data Bus Buffer - The data Bus Buffer
accepts inputs from the system bus and
generates control signals for the other D16750
functional blocks. Address bus ADDR(2:0)
selects one of the register to be read
from/written into. Both RD and WE signals are
active low, and are qualified by CS; RD and
WE are ignored unless the D16750 has been
selected by holding CS low.
Baud Generator - The D16750 contains a
programmable 16 bit baud generator that
divides clock input by a divisor in the range
between 1 and (2¹⁶–1). The output frequency
of the baud generator is 16× the baud rate.
The formula for the divisor is:
divisor = ^frequency
baudrate *16
Two 8-bit registers, called divisor latches DLL
and DLM, store the divisor in a 16-bit binary
format. These divisor latches must be loaded
during initialization of the D16750 in order to
ensure desired operation of the baud
generator. When either of the divisor latches
is loaded, a 16-bit baud counter is also loaded
on the CLK rising edge following the write to
DLL or DLM to prevent long counts on initial
load.
Modem Control Logic controls the interface
with the MODEM or data set (or a peripheral
device emulating a MODEM).
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