DFPAU-DP Datasheet, PDF (4/6 Pages) Digital Core Design – Floating Point Arithmetic Coprocessor Double Precision

Information about shifted-out bits are stored
for rounding process.
Control Coprocessor – manages execution
of all instructions and internal operation re-
quired to execute particular function.
Interface – makes interface between exter-
nal device and DFPAU-DP internal 32-bit
modules. It contains data, control and status
registers. It can be configured to work with 8-,
16- and 32-bit processors.
PERFORMANCE
The following table gives a survey about
the Core area and performance in the AL-
TERA® devices after Place & Route (all key
features have been included):
Device
Speed
grade
Logic Cells
F_max
CYCLONE
-6
3660
79 MHz
CYCLONE-II
-6
3630
71 MHz
STRATIX
-5
3660
84 MHz
STRATIX-II
-3
2800
110 MHz
Core performance in ALTERA® devices
DFPAU-DP floating point instructions per-
formance has been compared to standard C
library functions delivered with every com-
mercial C compiler. Each program was exe-
cuted in the same system environments.
Number of clock periods were measured be-
tween input data loading into work registers
and output result storing after operation.
The results are placed in table below. Im-
provement has been computed as number of:
(NIOS-II CLK) divided by (NIOS-II+DFPAU-
DP CLK), required to execute particular in-
struction.
IEEE-754 FP Instruction
Addition
Subtraction
Multiplication
Division
Square Root
Sine
Cosine
Tangent
Arcs Tangent
Average speed improvement:
Improvement
12.0
11.7
10.6
15.0
21.5
11.8
10.3
10.1
14.7
13.1
More details are available in core docu-
mentation.
The following table gives a survey about
the 32-bit NIOS-II+DFPAU-DP performance
compared to 32-bit NIOS-II.
Device
NIOS-II
NIOS-II+DFPAU (arithmetic)
NIOS-II+DFPAU (trigonometric)
NIOS-II+DFPAU (overall)
Improvement
1.0
14.1
11.7
13.1
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