DFPAU-DP Datasheet, PDF(3/6 Page) Digital Core Design – Floating Point Arithmetic Coprocessor Double Precision

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DFPAU-DP Datasheet, PDF (3/6 Pages) Digital Core Design – Floating Point Arithmetic Coprocessor Double Precision

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LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of

IP Core easy and simply.

Single Design license allows using IP Core in

single FPGA bitstream and ASIC implemen-

tation. It also permits FPGA prototyping be-

fore ASIC production.

Unlimited Designs license allows using IP

Core in unlimited number of FPGA bitstreams

and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time of use

limitations.

â Single Design license for

â VHDL, Verilog source code called HDL

Source

â Encrypted, or plain text EDIF called Netlist

â Unlimited Designs license for

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â Netlist

â Upgrade from

â Netlist to HDL Source

â Single Design to Unlimited Designs

SYMBOL

datai(31:0)1

addr(4:2)2

datao(31:0)1

irq

rst

clk

PINS DESCRIPTION

clk

rst

datai[31:0]1

addr[4:2]2

datao[31:0]1

irq

TYPE

DESCRIPTION

Input Global system clock

Input Global system reset

Input Chip select for read/write

Input Data bus input

Input Register address to read/write

Input Data write enable

Output Data bus output

Output Interrupt request indicator

1 â data bus can be configured as 8-, 16- or 32- bit

depends on processorâs bus size

2 â address bus is aligned to work with 8- (3:0), 16-

(3:1) or 32- (4:2) bit processors

BLOCK DIAGRAM

Mantissa â performs operations on mantissa

part of number. The addition, subtraction,

multiplication, division, square root, compari-

son and conversion operations are executed

in this module. It contains mantissas and

work registers.

datai(31:0)1

datao(31:0)1

irq

addr(4:2)2

Interface

Mantissa

Align

Exponent

Shifter

clk

rst

Control

Unit

Exponent â performs operations on expo-

nent part of number. The addition, subtrac-

tion, shifting, comparison and conversion

operations are executed in this module. It

contains exponents and work registers.

Align â performs the numbers analyze

against IEEE-754 standard compliance. In-

formation about the data classes are passed

as result to appropriate internal module.

Shifter â performs mantissa shifting during

normalization, denormalization operations.

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