DFPIC1655X Datasheet, PDF (3/7 Pages) Digital Core Design – High Performance Configurable 8-bit RISC Microcontroller

LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC implementa-
tion.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA bit-
streams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time restric-
tion except One Year license where time of
use is limited to 12 months.
● Single Design license for
○ VHDL, Verilog source code called HDL Sour-
ce
○ Encrypted, or plain text EDIF called Netlist
● One Year license for
○ Encrypted Netlist only
● Unlimited Designs license for
○ HDL Source
○ Netlist
● Upgrade from
○ HDL Source to Netlist
○ Single Design to Unlimited Designs
SYMBOL
clk
clkwdt
por
mclr
prgdata(13:0) prgaddr(15:0)
ramdatai(7:0)
intr
t0cki
portai(7:0)
portbi(7:0)
ramdatao(7:0)
ramaddr(8:0)
ramwe
ramoe
sleep
portao(7:0)
portbo(7:0)
trisa(7:0)
trisb(7:0)
docddatai
DoCD^TM Interface
docddatao
docdclk
prgdatao(13:0)
prgwe
PINS DESCRIPTION
PIN TYPE
DESCRIPTION
clk
clkwdt
input Global clock
input Watchdog clock
por
mclr
prgdata[13:0]
input Global reset Power On Reset
input User reset
input Data bus from program memory
ramdati[7:0]
intr
t0cki
input Data bus from int. data memory
input External interrupt
input Timer 0 input
portax[7:0]
docddatai
prgaddr[15:0]
input Port X input
input DoCD^TM Debugger input
output Program memory address bus
ramdatao[7:0]
ramaddr[8:0]
ramwe
output Data bus for internal data memory
output RAM address bus
output Data memory write
ramoe
sleep
portxo[7:0]
output Data memory output enable
output Sleep signal
output Port X output
trisx[7:0]
docddatao
docdclk
output Data direction pins for Port X
output DoCD^TM Debugger data output
output DoCD^TM Clock line
prgdatao[13:0] output Program Memory data output
prgwe
output Program Memory write enable
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.